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Si5310

Table 4. AC Characteristics (PLL Performance Characteristics)

(V

DD

= 2.5 V 卤5%, T

A

= 鈥?0 to 85 掳C)

Parameter

Jitter Tolerance

(MULTSEL = 0,

MULTOUT = 600 to 668 MHz)

Jitter Tolerance

(MULTSEL = 1,

MULTOUT = 150 to 167 MHz)

Jitter Generation (MULTOUT, CLKOUT)

(MULTSEL = 0,

MULTOUT = 600 to 668 MHz)*

(measurement BW = 12kHz to 1MHz)

Symbol

J

TOL(PP)

Test Condition

Min

Typ

Max

Unit

See Table 5

J

TOL(PP)

See Table 6

J

GEN(rms)

Clock Input (MHz) =

37.500 to 41.750

Clock Input (MHz) =

75.000 to 83.500

Clock Input (MHz) =

150.000 to 167.000

Clock Input (MHz) =

300.000 to 334.000

Clock Input (MHz) =

600.000 to 668.000

鈥?/div>

2.5

1.6

0.9

0.6

0.4

8.5

5.0

3.7

2.3

1.1

75

150

300

600

1200

5.4

3.1

1.6

1.3

0.8

34.0

19.7

15.2

3.0

105

210

420

840

1680

ps

rms

ps

rms

ps

rms

ps

rms

ps

rms

ps

rms

ps

rms

ps

rms

ps

rms

ps

rms

kHz

Jitter Generation (MULTOUT, CLKOUT)

(MULTSEL = 1,

MULTOUT = 150 to 167 MHz)*

(measurement BW = 12kHz to 1MHz)

J

GEN(rms)

Clock Input (MHz) =

9.375 to 10.438

Clock Input (MHz) =

18.750 to 20.875

Clock Input (MHz) =

37.500 to 41.750

Clock Input (MHz) =

75.000 to 83.500

Clock Input (MHz) =

150.000 to 167.000

Jitter Transfer Bandwidth

(MULTSEL = 0,

MULTOUT = 600 to 668 MHz)*

J

BW

Clock Input (MHz) =

37.500 to 41.750

Clock Input (MHz) =

75.000 to 83.500

Clock Input (MHz) =

150.000 to 167.000

Clock Input (MHz) =

300.000 to 334.000

Clock Input (MHz) =

600.000 to 668.000

*Note:

See PLL Performance section of this document for test descriptions.

8

Rev. 1.2

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