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M24C04-WMN6 Datasheet

  • M24C04-WMN6

  • IC EEPROM 4KBIT 400KHZ 8SOIC

  • 437.20KB

  • 29页

  • STMicroelectronics   STMicroelectronics

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M24C16, M24C08, M24C04, M24C02, M24C01
Table 13. AC Characteristics (M24Cxx-W)
Test conditions specified in
Table 6.
and
Table 11.
Symbol
f
C
t
CHCL
t
CLCH
t
DL1DL2 2
t
DXCX
t
CLDX
t
CLQX
t
CLQV 3
t
CHDX 1
t
DLCL
t
CHDH
t
DHDL
t
W 4
Note: 1.
2.
3.
4.
Alt.
f
SCL
t
HIGH
t
LOW
t
F
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
WR
Clock Frequency
Parameter
Min.
Max.
400
Unit
kHz
ns
ns
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
Time between Stop Condition and Next Start Condition
Write Time
600
1300
20
100
0
200
200
600
600
600
1300
5
900
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
For a reSTART condition, or following a Write cycle.
Sampled only, not 100% tested.
To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Previous devices bearing the process letter 鈥淟鈥?in the package marking guarantee a maximum write time of 10ms. For more infor-
mation about these devices and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/
EE/0061 and 0062 (PCEE0061 and PCEE0062).
Table 14. AC Characteristics (M24Cxx-R)
Test conditions specified in
Table 7.
and
Table 10.
Symbol
f
C
t
CHCL
t
CLCH
t
DL1DL2 2
t
DXCX
t
CLDX
t
CLQX
t
CLQV 3
t
CHDX 1
t
DLCL
t
CHDH
t
DHDL
t
W
Note: 1.
2.
3.
4.
Alt.
f
SCL
t
HIGH
t
LOW
t
F
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
WR
Clock Frequency
Parameter
Min.
4
Max.
4
400
Unit
kHz
ns
ns
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
Time between Stop Condition and Next Start Condition
Write Time
600
1300
20
100
0
200
200
600
600
600
1300
10
900
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
For a reSTART condition, or following a Write cycle.
Sampled only, not 100% tested.
To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
This is preliminary information.
16/25

M24C04-WMN6 产品属性

  • 2,000

  • 集成电路 (IC)

  • 存储器

  • -

  • EEPROMs - 串行

  • EEPROM

  • 4K (512 x 8)

  • 400kHz

  • I²C，2 线串口

  • 2.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 8-SOIC（0.154"，3.90mm 宽）

  • 8-SO

  • 管件

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