SC26C92C1A-S Datasheet

IC型号：
SC26C92C1A-S
文件大小：
221.70KB
PDF页数：
31页
芯片厂家：
Philips

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Philips Semiconductors

Product specification

Dual universal asynchronous receiver/transmitter (DUART)

SC26C92

Block Diagram

The SC26C92 DUART consists of the following eight major sections:

data bus buffer, operation control, interrupt control, timing,

communications Channels A and B, input port and output port.

Refer to the Block Diagram.

Data Bus Buffer

The data bus buffer provides the interface between the external and

internal data buses. It is controlled by the operation control block to

allow read and write operations to take place between the controlling

CPU and the DUART.

Counter鈥揟imer

The Counter/Timer is a programmable 16鈥揵it divider that is used for

generating miscellaneous clocks or generating timeout periods.

These clocks may be used by any or all of the receivers and trans-

mitters in the DUART or may be directed to an I/O pin for miscella-

neous use.

Counter/Timer programming

The counter timer is a 16鈥揵it programmable divider that operates in

one of three modes: counter, timer, and time out.

Operation Control

The operation control logic receives operation commands from the

CPU and generates appropriate signals to internal sections to

control device operation. It contains address decoding and read and

write circuits to permit communications with the microprocessor via

the data bus.

鈥?/div>

Timer mode generates a square wave.

鈥?/div>

Counter mode generates a time delay.

鈥?/div>

Time out mode counts time between received characters.

Interrupt Control

A single active-Low interrupt output (INTRN) is provided which is

activated upon the occurrence of any of eight internal events.

Associated with the interrupt system are the Interrupt Mask Register

(IMR) and the Interrupt Status Register (ISR). The IMR can be

programmed to select only certain conditions to cause INTRN to be

asserted. The ISR can be read by the CPU to determine all

currently active interrupting conditions.

Outputs OP3-OP7 can be programmed to provide discrete interrupt

outputs for the transmitter, receivers, and counter/timer.

When OP3 to OP7 are programmed as interrupts, their output

buffers are changed to the open drain active low configuration.

These pins may be used for DMA and modem control.

The C/T uses the numbers loaded into the Counter/Timer Lower

its divisor. The counter timer is controlled with six commands: Start/

Stop C/T, Read/Write Counter/Timer lower register and Read/Write

Counter/Timer upper register. These commands have slight differ-

ences depending on the mode of operation. Please see the detail of

the commands under the CTPL/CTPU register descriptions.

Baud Rate Generation with the C/T

When the timer is selected as baud rates for receiver or transmitter

via the Clock Select register their output will be configured as a 16x

clock. Therefore one needs to program the timer to generate a

clock 16 times faster than the data rate. The formula for calculating

鈥檔鈥? the number loaded to the CTPU and CTPL registers, based on a

particular input clock frequency is shown below.

For the timer mode the formula is as follows:

TIMING CIRCUITS

Crystal Clock

The timing block consists of a crystal oscillator, a baud rate

generator, a programmable 16-bit counter/timer, and four clock

selectors. The crystal oscillator operates directly from a crystal

connected across the X1/CLK and X2 inputs. If an external clock of

the appropriate frequency is available, it may be connected to

X1/CLK. The clock serves as the basic timing reference for the

Baud Rate Generator (BRG), the counter/timer, and other internal

circuits. A clock signal within the limits specified in the

specifications section of this data sheet must always be supplied to

the DUART.

If an external is used instead of a crystal, X1 should be driven using

a configuration similar to the one in Figure 7.

Clockinputfrequency

16 Baudratedesired

NOTE:

鈥榥鈥?may not assume values of 0 and 1.

The frequency generated from the above formula will be at a rate 16

times faster than the desired baud rate. The transmitter and receiv-

er state machines include divide by 16 circuits, which provide the

final frequency and provide various timing edges used in the qualify-

ing the serial data bit stream. Often this division will result in a non鈥?/div>

integer value: 26.3 for example. One may only program integer

numbers to a digital divider. There for 26 would be chosen. If 26.7

were the result of the division then 27 would be chosen. This gives

a baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage

error of 1.14% or 1.12% respectively, well within the ability of the

asynchronous mode of operation. Higher input frequency to the

counter reduces the error effect of the fractional division

One should be cautious about the assumed benign effects of small

errors since the other receiver or transmitter with which one is com-

municating may also have a small error in the precise baud rate. In

a 鈥漜lean鈥?communications environment using one start bit, eight data

bits and one stop bit the total difference allowed between the trans-

mitter and receiver frequency is approximately 4.6%. Less than

eight data bits will increase this percentage.

BRG

The baud rate generator operates from the oscillator or external

clock input and is capable of generating 27 commonly used data

communications baud rates ranging from 50 to 38.4K baud.

Programming bit 0 of MR0 to a 鈥?鈥?gives additional baud rates to

230.4kB. These will be in the 16X mode. A 3.6864MHz crystal or

external clock must be used to get the standard baud rates. The

clock outputs from the BRG are at 16X the actual baud rate. The

counter/timer can be used as a timer to produce a 16X clock for any

other baud rate by counting down the crystal clock or an external

clock. The four clock selectors allow the independent selection, for

each receiver and transmitter, of any of these baud rates or external

timing signal.

Communications Channels A and B

Each communications channel of the SC26C92 comprises a

full-duplex asynchronous receiver/transmitter (UART). The

2000 Jan 31

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SC26C92C1A-S 产品属性

制造商
NXP
产品种类
UART 接口集成电路
通道数量
2
数据速率
230.4 Kbps
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
电源电流
10 mA
最大工作温度
+ 70 C
最小工作温度
- 40 C
封装 / 箱体
PLCC-44
封装
Tube
安装风格
SMD/SMT
工作电源电压
5 V
工厂包装数量
26
零件号别名
SC26C92C1A,529

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