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M93C86-MN6T Datasheet

  • M93C86-MN6T

  • IC EEPROM 16KBIT 2MHZ 8SOIC

  • 590.00KB

  • 31页

  • STMicroelectronics   STMicroelectronics

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READY/BUSY status
M93C86, M93C76, M93C66, M93C56, M93C46
6
READY/BUSY status
While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.
(Please note, though, that there is an initial delay, of t
SLSH
, before this status information
becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write
cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.
7
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
8
Common I/O operation
Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a
current limiting resistor, to form a common, single-wire data bus. Some precautions must be
taken when operating the memory in this way, mostly to prevent a short circuit current from
flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output
(Q). Please see the application note
AN394
for details.
18/37

M93C86-MN6T 产品属性

  • 2,500

  • 集成电路 (IC)

  • 存储器

  • -

  • EEPROMs - 串行

  • EEPROM

  • 16K（2K x 8 或 1K x 16）

  • 2MHz

  • Microwire 3 线串行

  • 4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 8-SOIC（0.154"，3.90mm 宽）

  • 8-SO

  • 带卷 (TR)

  • 497-1936-2

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