鈥?/div>
60
DT0
DT4
o
o
1
16
1
16
TD0
o
o
o
o
o
TIE
DT_ON
DT6
o
o
8
128
8
128
TE
o
o
o
o
o
o
o
4
64
4
64
TI/TP
o
o
o
o
o
CS1 Controller
CTEMP CDT_ON
FOUT divider ratio setting register
FOUT divider ratio setting register
Alarm control
o
FE
FD2
o
TEST TEMP 2000 1000
TEST TEMP
TEST TEMP
Control registers
Bank Sel 1 Bank Sel 0 STOP BUSY/ADJ
Control register
Bank Sel 1 Bank Sel 0 STOP BUSY/ADJ
Bank Sel 1 Bank Sel 0 STOP BUSY/ADJ
Reading data
t
RC
A
0
to A
3
AC characteristics
鈥ND=0 V, Ta= -40
掳C
to + 85
掳C
鈥nput conditions: VI= 0.5 x VDD, VO= 0.5 x V
DD
鈥utput load: CL= 100 pF (tACC,tACS,tARD)
t
OH
t
ACC
t
ACS
CS
0
Item
Read cycle time
Address access time
CE access time
RD access time
CE output set time
CE output floating
RD output set time
RD output floating
Output hold time
Write cycle time
Chip select time
Address valid end of write
Address setup time
Address hold time
Write pulse width
Input data set time
Input data hold time
FOUT output frequency duty
V
DD
=2.4 to 3.6 V V
DD
=4.5 to 5.5 V
Symbol
Condition
t
RC
t
ACC
t
ACS
t
ARD
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
OH
t
WC
t
CW
t
AW
t
AS
t
WR
t
WP
t
DW
t
DH
DUTY
t
CLZ
CS
1
t
CHZ
t
ACS
t
CLZ
t
ARD
t
CHZ
RD
t
OLZ
D
0
to D
3
t
OHZ
Writing data (CS Control)
t
WC
A
0
to A
3
t
AW
t
CW
CS
0
t
WR
t
AS
CS
1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Min.
150
鈥?/div>
鈥?/div>
鈥?/div>
5
鈥?/div>
5
鈥?/div>
10
150
140
140
0
0
130
80
0
40
Max.
鈥?/div>
150
150
100
鈥?/div>
60
鈥?/div>
60
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
60
Min.
85
鈥?/div>
鈥?/div>
鈥?/div>
3
鈥?/div>
3
鈥?/div>
5
85
70
70
0
0
65
35
0
40
Unit
n
s
n
s
n
s
n
s
n
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
WR
Block diagram
t
DW
t
DH
32.768 kHz
OSC
VTEMP
F
OUT
F
CON
*2
7301SF
*1
FOUT=
32.768 kHz
Control line
Degital Trimming
REGISTER
D
0
to D
3
DIVIDER
Writing data (WR Control)
t
wC
A
0
to A
3
Temperature
Sensor
*1
FOUT CONTROLLER
CLOCK and CALENDAR
TIMER REGISTER
7301DG
t
AW
CS
0
t
WR
IRQ
INTERRUPTS
CONTROLLER
t
AS
CS
1
A
0
to A
3
D
0
to D
3
WR
RD
ALARM REGISTER
BUS
INTERFACE
CIRCUIT
t
WP
WR
CS0
CS1
CONTROL REGISTER
and
SYSTEM CONTROLLER
t
DW
D
0
to D
3
t
DH
*This is a block diagram for RTC-7301SF.
Be aware that RTC-7301DG differs according to the following 2 points.
*1)The VTEMP output is not connected to an external pin.
*2)The FCON input pin is not connected to an external pin, but is fixed at "H" internally.
bit 0
92
RTC-7301DG 产品属性
年：月：日：时：分：秒
12小时/24小时
RTC
平行
2.4V 到 5.5V
DIP
18
-40°C 到 +85°C
No SVHC (19-Dec-2011)
7301
DIP
-40°C
85°C
Parallel
Parallel
32.768kHz
固定周期定时器中断
5.5V
2.4V
RTC
DIP
通孔安装
7
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