330鈩?/div>
1W
2N3904
PWS725A/726A
15
2N3904
16
19
(1)
Buffer
鈥揤
CC
TTL
2
SYNC
Signal
(2)
Keep Connection
Short
NOTE: (1) Units to be synchronized
should have a lower free-running
frequency than the master unit.
Grounding Frequency Adjust (pin 19)
will shift the free-running frequency
to approximately 400kHz.
Slave
PWS725A/726A
15
16
19
(1)
To Other
PWS725A/726A
Converters
NOTES: (1) Units to be synchronized
should have a lower free-running
frequency than the TTL signal.
Grounding Frequency Adjust (Pin 19)
will shift the free-running frequency
to approximately 400kHz. (2) The TTL
SYNC signal can have a frequency
range of 450kHz to 1.5MHz.
PWS725A/726A
15
16
19
(1)
FIGURE 2. Synchronization of Multiple PWS725As or
PWS726As from a Master Converter.
switches operating in their safe operating area under fault
conditions or excessive loads. When either of these condi-
tions occur, the peak input current exceeds a safe limit. The
result is an approximate 5% duty cycle, 300碌s drive period
to the MOSFET switches. This protects the internal MOSFET
switches as well as the external load from any thermal
damage. When the fault or excessive load is removed, the
converter resumes normal operation. A delay period of
approximately 50碌s incorporated in the current sensing
circuitry allows the output filter capacitors to fully charge
after a fault is removed. This delay period corresponds to a
filter capacitance of no more than 1碌F at either of the output
pins. This provides full protection of the MOSFET switches
and also sufficiently filters the output ripple voltage (see
specification table). The current sensing circuitry is de-
signed to provide thermal protection for the MOSFET
switches over the operating temperature range as well. The
low thermal resistance for the package (
胃
JC
= 10掳C/W)
ensures safe operation under rated conditions. When these
rated conditions are exceeded, the unit will go into its
shutdown mode.
An optional potentiometer can be connected between the
two FREQUENCY ADJUST pins to trim the oscillator
operating frequency
卤10%
(see Figure 4). Care should be
taken when trimming the frequency near the low frequency
range. If the frequency is trimmed too low, the peak induc-
tive currents in the primary will trip the input current
sensing circuitry to protect the MOSFET switches from
these peak inductive currents.
The ENABLE pin allows external control of output power.
When this pin is pulled low, output power is disabled. Logic
thresholds are TTL compatible. When not used, the Enable
input may be left open or tied to V
IN
(pin 16).
5
To Other
PWS725A/726A
Converters
FIGURE 3. Synchronization of Multiple PWS725As or
PWS726As from an External TTL Signal.
PWS725A/726A
Monitor frequency with scope
or frequency counter (use
low C probe).
15
19
20k鈩?/div>
(1)
20
Frequency
Increase
+5V
BE
+4V
BE
1.25碌s Nominal
SYNC Signal
NOTE: (1) For nominal 800kHz operation, leave
pins 19 and 20 open.
FIGURE 4. Frequency Adjustment Procedure.
OUTPUT CURRENT RATING
The total current which can be drawn from the PWS725A
or PWS726A is a function of total power being drawn from
both outputs (see Functional Diagram). If one output is not
used, then maximum current can be drawn from the other
output. If both outputs are loaded, the total current must be
limited such that:
|I
L
+| + |I
L
鈥搢
鈮?/div>
80mA
It should be noted that many analog circuit functions do not
simultaneously draw full rated current from both the posi-
tive and negatives supplies. For example, an operational
amplifier may draw 13mA from the positive supply under
庐
PWS725A/726A
1
2
3
4
5
6
