MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383A 鈭?OCTOBER 2003 鈭?REVISED AUGUST 2004
flash memory (continued)
8KB
16KB
32KB
0FFFFh
Segment 0
With Interrupt Vectors
Segment 1
0FC00h 0FC00h 0FC00h
0FBFFh 0FBFFh 0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FFFFh 0FFFFh
0FE00h 0FE00h 0FE00h
0FDFFh 0FDFFh 0FDFFh
Main Memory
0E400h
0C400h
08400h
083FFh
08200h
081FFh
Segment n
08000h
010FFh
Segment A
01080h
0107Fh
Segment B
01000h
Information Memory
Segment n鈭?
0E3FFh 0C3FFh
0E200h 0C200h
0E1FFh 0C1FFh
0E000h
010FFh
01080h
0107Fh
01000h
0C000h
010FFh
01080h
0107Fh
01000h
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the
MSP430x4xx Family User鈥檚 Guide,
literature
number SLAU056.
oscillator and system clock
The clock system in the MSP430xW42x family of devices is supported by the FLL+ module that includes support
for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6
碌s.
The FLL+ module
provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
11
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