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IDT79RC32T355-180DH Datasheet

  • IDT79RC32T355-180DH

  • IDT Interprise Integrated Communications Processor

  • 991.93KB

  • 47页

  • IDT

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IDT 79RC32355
AC Timing Definitions
Below are examples of the AC timing characteristics used throughout this document.
Tlow
Tperiod
clock
Tdo
Output signal 1
Tzd
Output signal 2
Tsu
Input Signal 1
Tpw
Signal
Thld
Tdz
Tdo
Tjitter
Trise
Tfall
Thigh
Figure 5 AC Timing Definitions Waveform
Symbol
Tperiod
Tlow
Thigh
Trise
Tfall
Tjitter
Tdo
Tzd
Tdz
Tsu
Thld
Tpw
Clock period.
Clock low. Amount of time the clock is low in one clock period.
Clock high. Amount of time the clock is high in one clock period.
Rise time. Low to high transition time.
Fall time. High to low transition time.
Definition
Jitter. Amount of time the reference clock (or signal) edge can vary on either the rising or falling edges.
Data out. Amount of time after the reference clock edge that the output will become valid. The minimum time represents the data output hold.
The maximum time represents the earliest time the designer can use the data.
Z state to data valid. Amount of time after the reference clock edge that the tri-stated output takes to become valid.
Data valid to Z state. Amount of time after the reference clock edge that the valid output takes to become tri-stated.
Input set-up. Amount of time before the reference clock edge that the input must be valid.
Input hold. Amount of time after the reference clock edge that the input must remain valid.
Pulse width. Amount of time the input or output is active.
Table 4 AC Timing Definitions
16 of 47
May 25, 2004

IDT79RC32T355-180DH 产品属性

  • 24

  • 集成电路 (IC)

  • 嵌入式 - 微处理器

  • Interprise™

  • RISC 32-位

  • -

  • 180MHz

  • 2.5V

  • 表面贴装

  • 208-BFQFP

  • 208-PQFP（28x28）

  • 托盘

  • 79RC32T355-180DH

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