IDT79RC32T355-180DH Datasheet

  • IDT79RC32T355-180DH

  • IDT Interprise Integrated Communications Processor

  • 991.93KB

  • 47页

  • IDT

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IDT 79RC32355
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CLKP
SYSCLKP
COLDRSTN
Trise1
Tdo2
RSTN
Thld3
BOOT VECT
MDATA[31:0]
FFFF_FFFF
BDIRN
BOEN[0]
>= 100 ms
Tpw1
>=10ms
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
*
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
*
*
Selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset).
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COLDRSTN asserted by external logic.
The RC32355 asserts RSTN, asserts BOEN[0] low, drives BDIRN low, and tri-states the data bus in response.
External logic begins driving valid boot configuration vector on the data bus, and the RC32355 starts sampling it.
External logic negates COLDRSTN and tri-states the boot configuration vector on MDATA[15:0]. The boot configuration vector must not be tri-stated before COLDRSTN is deas-
serted. The RC32355 stops sampling the boot configuration vector.
The RC32355 starts driving the data bus, MDATA[31:0], deasserts BOEN[0] high, and drives BDIRN high.
SYSCLKP may be held constant after this point if Hold SYSCLKP Constant is selected in the boot configuration vector.
RSTN negated by RC32355.
CPU begins executing by taking MIPS reset exception, and the RC32355 starts sampling RSTN as a warm reset input.
Figure 6 Cold Reset AC Timing Waveform
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CLKP
COLDRSTN
RSTN
MDATA[31:0]
Mem Control Signals
Active
Deasserted
FFFF_FFFF
Active
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
*
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
*
(RSTN ignored during this period
to allow pull-up to drive signal high)
*
Selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset).
1.
2.
3.
4.
5.
Warm reset condition caused by either RSTN asserted, write to reset register, or bus transaction timer time-out. The RC32355 asserts RSTN output low in response.
The RC32355 tri-states the data bus, MDATA[31:0], and deasserts all memory control signals, such as RASN, CASN, RWN, OEN, etc.
The RC32355 deasserts RSTN.
The RC32355 starts driving the data bus, MDATA[31:0], again, but does not sample the RSTN input.
CPU begins executing by taking a MIPS soft reset exception and also starts sampling the RSTN input again.
Figure 7 Warm Reset AC Timing Waveform
18 of 47
May 25, 2004

IDT79RC32T355-180DH 产品属性

  • 24

  • 集成电路 (IC)

  • 嵌入式 - 微处理器

  • Interprise™

  • RISC 32-位

  • -

  • 180MHz

  • 2.5V

  • 表面贴装

  • 208-BFQFP

  • 208-PQFP(28x28)

  • 托盘

  • 79RC32T355-180DH

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