鈥?/div>
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Figure 11
Figure 12
Table 6 Memory and Peripheral Bus AC Timing Characteristics (Part 2 of 2)
Note:
The RC32355 provides bus turnaround cycles to prevent bus contention when going from a read to write, write to read, and during
external bus ownership. For example, there are no cycles where an external device and the RC32355 are both driving. See the chapters
鈥淒evice Controller,鈥?鈥淪ynchronous DRAM Controller,鈥?and 鈥淏us Arbitration鈥?in the RC32355 User Reference Manual.
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May 25, 2004