鈥?/div>
JTAG_TMS, JTAG_TDI,
JTAG_TRST_N
JTAG_TDO
Tsu3
Thld3
Tdo4
Tdo5
JTAG_TCK rising
3.0
1.0
JTAG_TCK falling
2.0
EJTAG_DCLK rising -0.7
2
none
JTAG_TCK rising
100
2
JTAG_TRST_N
Tpw6
Tsu6
EJTAG_PCST[2:0]
1.
2.
Tdo7
EJTAG_DCLK rising -0.3
2
EJTAG_DCLK is equal to the internal CPU pipeline clock.
A negative delay denotes the amount of time before the reference clock edge.
Table 15 JTAG AC Timing Characteristics
Tperiod1
JTAG_TCK
Trise1
EJTAG_DCLK
Tlow1
Tfall1
Thigh1
Thigh2
Trise2
JTAG_TMS,
JTAG_TDI
Tsu3
JTAG_TDO
TDO
Tdo4
EJTAG_PCST
Tdo7
JTAG_TRST_N
EJTAG_TRST_N
Tpw6
Figure 20 JTAG AC Timing Waveform
Thld3
TDO
Tdo5
PCST
TPC
Tfall2
EJTAG TPC, TCST capture
Tperiod2
Tlow2
Tsu6
36 of 47
May 25, 2004