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IDT79RC32T355-180DH Datasheet

  • IDT79RC32T355-180DH

  • IDT Interprise Integrated Communications Processor

  • 991.93KB

  • 47页

  • IDT

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IDT 79RC32355
Name
RWN
OEN
BWEN[3:0]
Type I/O Type
O
O
O
Description
High Drive
Read or Write.
This signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write
transaction. A high level indicates a read from an external device, a low level indicates a write to an external device.
High Drive
Output Enable.
This signal is asserted low when data should be driven by an external device during device read transac-
tions on the memory and peripheral bus.
High Drive
SDRAM Byte Enable Mask or Memory and I/O Byte Write Enables.
These signals are used as data input/output masks
during SDRAM transactions and as byte write enable signals during device controller transactions on the memory and
peripheral bus. They are active low.
BWEN[0] corresponds to byte lane MDATA[7:0].
BWEN[1] corresponds to byte lane MDATA[15:8].
BWEN[2] corresponds to byte lane MDATA[23:16].
BWEN[3] corresponds to byte lane MDATA[31:24].
High Drive
SDRAM Chip Select.
These signals are used to select the SDRAM device on the memory and peripheral bus. Each bit is
asserted low during an access to the selected SDRAM.
High Drive
SDRAM Row Address Strobe.
The row address strobe asserted low during memory and peripheral bus SDRAM transac-
tions.
High Drive
SDRAM Column Address Strobe.
The column address strobe asserted low during memory and peripheral bus SDRAM
transactions.
High Drive
SDRAM Write Enable.
Asserted low during memory and peripheral bus SDRAM write transactions.
Low Drive
SDRAM Clock Enable.
Asserted high during active SDRAM clock cycles.
Primary function: General Purpose I/O, GPIOP[21].
STI
SDRAM Clock Input.
This clock input is a delayed version of SYSCLKP. SDRAM read data is sampled into the RC32355
on the rising edge of this clock.
ATM PHY Inputs.
These pins are the inputs for the ATM interface.
SDCSN[1:0]
RASN
CASN
SDWEN
CKENP
SDCLKINP
ATM Interface
ATMINP[11:0]
ATMIOP[1:0]
ATMOUTP[9:0]
TXADDR[1:0]
O
O
O
O
O
I
I
I/O
O
O
STI
Low Drive
ATM PHY Bidirectional Signals.
These pins are the bidirectional pins for the ATM interface.
with STI
Low Drive
ATM PHY Outputs.
These pins are the outputs for the ATM interface.
Low Drive
ATM Transmit Address [1:0].
2-bit address bus used for transmission in Utopia-2 mode.
TXADDR[0] Primary function: General purpose I/O, GPIOP[22].
TXADDR[1] Primary function: General purpose I/O, GPIOP[23].
Low Drive
ATM Receive Address [1:0].
2-bit address bus for receiving in Utopia-2 mode.
RXADDR[0] Primary function: General purpose I/O, GPIOP[24].
RXADDR[1] Primary function: General purpose I/O, GPIOP[25].
High Drive
TDM Serial Data Output.
Serial data is driven by the RC32355 on this signal during an active output time slot. During inac-
tive time slots this signal is tri-stated.
Primary function: General purpose I/O, GPIOP[32].
STI
TDM Serial Data Input.
Serial data is received by the RC32355 on this signal during active input time slots.
Primary function: General purpose I/O, GPIOP[33].
RXADDR[1:0]
O
TDM Bus
TDMDOP
O
TDMDIP
TDMFP
I
I/O
High Drive
TDM Frame Signal.
A transition on this signal, the active polarity of which is programmable, delineates the start of a new
TDM bus frame. TDMFP is driven if the RC32355 is a master, and is received if it is a slave.
Primary function: General purpose I/O, GPIOP[34].
STI
TDM Clock.
This input clock controls the rate at which data is sent and received on the TDM bus.
Primary function: General purpose I/O, GPIOP[35].
Table 1 Pin Descriptions (Part 2 of 8)
TDMCLKP
I
6 of 47
May 25, 2004

IDT79RC32T355-180DH 产品属性

  • 24

  • 集成电路 (IC)

  • 嵌入式 - 微处理器

  • Interprise™

  • RISC 32-位

  • -

  • 180MHz

  • 2.5V

  • 表面贴装

  • 208-BFQFP

  • 208-PQFP（28x28）

  • 托盘

  • 79RC32T355-180DH

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