您的位置：维库电子市场网 > Datasheet > IDT79RC32T355-180DH

IDT79RC32T355-180DH Datasheet

  • IDT79RC32T355-180DH

  • IDT Interprise Integrated Communications Processor

  • 991.93KB

  • 47页

  • IDT

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

IDT 79RC32355
Name
DMAREQN
DMADONEN
Type I/O Type
I
I
STI
STI
Description
External DMA Device Request.
The external DMA device asserts this pin low to request DMA service.
Primary function: General purpose I/O, GPIOP[18]. At reset, this pin defaults to primary function GPIOP[18].
External DMA Device Done.
The external DMA device asserts this signal low to inform the RC32355 that it is done with
the current DMA transaction.
Primary function: General purpose I/O, GPIOP[19]. At reset, this pin defaults to primary function GPIOP[19].
USB Clock.
48 MHz clock input used as time base for the USB interface.
USB D- Data Line.
This is the negative differential USB data signal.
USB D+ Data Line.
This is the positive differential USB data signal.
USB
USBCLKP
USBDN
USBDP
USBSOF
Ethernet
MIICOLP
MIICRSP
MIIMDCP
MIIMDIOP
MIIRXCLKP
MIIRXDP[3:0]
MIIRXDVP
MIIRXERP
MIITXCLKP
MIITXDP[3:0]
MIITXENP
MIITXERP
I
2
C
SCLP
I/O
Low Drive
I
2
C Interface Clock.
An external pull-up is required on SCLP, see the I
2
C spec.
2
with STI Primary function: General purpose I/O, GPIOP[15]. At reset, this pin defaults to primary function GPIOP[15].
Low Drive
I
2
C Interface Data Pin.
An external pull-up is required on SDAP, see the I
2
C spec.
2
with STI Primary function: General purpose I/O, GPIOP[14]. At reset, this pin defaults to primary function GPIOP[14].
I
I
O
I/O
I
I
I
I
I
O
O
O
STI
STI
MII Collision Detected.
This signal is asserted by the ethernet PHY when a collision is detected.
MII Carrier Sense.
This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle.
I
I/O
I/O
O
STI
USB
USB
Low Drive
USB start of frame.
Primary function: General Purpose I/O, GPIOP[20]. At reset, this pin defaults to primary function GPIOP[20].
Low Drive
MII Management Data Clock.
This signal is used as a timing reference for transmission of data on the management inter-
face.
Low Drive
MII Management Data.
This bidirectional signal is used to transfer data between the station management entity and the
with STI ethernet PHY.
STI
STI
STI
STI
STI
MII Receive Clock.
This clock is a continuous clock that provides a timing reference for the reception of data.
MII Receive Data.
This nibble wide data bus contains the data received by the ethernet PHY.
MII Receive Data Valid.
The assertion of this signal indicates that valid receive data is in the MII receive data bus.
MII Receive Error.
The assertion of this signal indicates that an error was detected somewhere in the ethernet frame cur-
rently being sent in the MII receive data bus.
MII Transmit Clock.
This clock is a continuous clock that provides a timing reference for the transfer of transmit data.
Low Drive
MII Transmit Data.
This nibble wide data bus contains the data to be transmitted.
Low Drive
MII Transmit Enable.
The assertion of this signal indicates that data is present on the MII for transmission.
Low Drive
MII Transmit Coding Error.
When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols
which are not valid data or delimiters.
SDAP
I/O
EJTAG
JTAG_TCK
JTAG_TDI
I
I
STI
STI
JTAG Clock.
This is an input test clock, used to shift data into or out of the boundary scan logic. This signal requires an
external resistor, listed in Table 16.
JTAG Data Input.
This is the serial data shifted into the boundary scan logic. This signal requires an external resistor,
listed in Table 16. This is also used to input EJTAG_DINTN during EJTAG/ICE mode. EJTAG_DINTN is an interrupt to
switch the PC trace mode off.
JTAG_TDO
O
Low Drive
JTAG Data Output.
This is the serial data shifted out from the boundary scan logic. When no data is being shifted out, this
signal is tri-stated. This signal requires an external resistor, listed in Table 16. This is also used to output the EJTAG_TPC
during EJTAG/ICE mode. EJTAG_TPC is the non-sequential program counter output.
Table 1 Pin Descriptions (Part 5 of 8)
9 of 47
May 25, 2004

IDT79RC32T355-180DH 产品属性

  • 24

  • 集成电路 (IC)

  • 嵌入式 - 微处理器

  • Interprise™

  • RISC 32-位

  • -

  • 180MHz

  • 2.5V

  • 表面贴装

  • 208-BFQFP

  • 208-PQFP（28x28）

  • 托盘

  • 79RC32T355-180DH

IDT79RC32T355-180DH相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！