256-Mbit J3 (x8/x16)
3.3
VF-BGA (J3) Package
Figure 5. Intel StrataFlash
庐
Memory (J3) VF BGA Mechanical Specifications
B a ll A 1
C o rn e r
D
S1
B all A1
C o rn e r
S2
1
A
B
C
E
D
E
F
2
3
4
5
6
7
8
A
B
C
D
E
F
b
e
8
7
6
5
4
3
2
1
T o p V ie w - B u m p S id e D o w n
B o tt o m V ie w - B a ll S id e U p
A1
A2
A
S e a t in g
P la n e
S id e V ie w
N o te : D r a w in g n o t t o s ca le
Y
D im e n s io n s T a b le
M illim e te rs
In ch es
Sym b ol
M in
Nom
M a x N o te s
M in
Pa c k a g e H e ig h t
A
1.000
0 .1 5 0
0 .0 0 5 9
Ba ll H e ig h t
A
1
Pa c k a g e B o d y T h ic k n e s s
A
2
0 .6 6 5
Ba ll (L e a d ) W id th
b
0 .3 2 5
0 .3 7 5
0.425
0 .0 1 2 8
D
7 .1 8 6
7 .2 8 6
7.386
1
0 .2 8 2 9
Pa c k a g e B o d y L e n g t h
E
1 0 .7 5 0
10.850
1 0 .9 5 0
1
0 .4 2 3 2
Pitc h
[e]
0 .7 5 0
Ba ll (L e a d ) C o u n t
N
48
Se a tin g P la n e C o p la n a r ity
Y
0.100
Co r n e r to B a ll A 1 D is ta n c e A lo n g D
S
1
0 .9 1 8
1 .0 1 8
1.118
1
0 .0 3 6 1
Co r n e r to B a ll A 1 D is ta n c e A lo n g E
S
2
3 .4 5 0
3 .5 5 0
3.650
1
0 .1 3 5 8
N o te : ( 1 ) P a c k a g e d im e n s io n s a re f o r r e f e re n c e o n ly . T h e s e d im e n s io n s a re e s t im a te s b a s e d o n d ie s iz e ,
a n d a r e su bj e c t t o c h a ng e .
N om
M ax
0 .0 3 9 4
0 .0 2 6 2
0 .0 1 4 8
0 .2 8 6 8
0 .4 2 7 2
0 .0 2 9 5
48
0 .0 4 0 1
0 .1 3 9 8
0 .0 1 6 7
0 .2 9 0 8
0 .4 3 1 1
0 .0 0 3 9
0 .0 4 4 0
0 .1 4 3 7
NOTES:
1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web
page at; www.intel.com/design/packtech/index.htm
2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page
at; www.intel.com/design/packtech/index.htm
Datasheet
13