E28F640J3C-150 Datasheet

  • E28F640J3C-150

  • Intel StrataFlash Memory (J3)

  • 909.85KB

  • 72页

  • INTEL   INTEL

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256-Mbit J3 (x8/x16)
0606_16
NOTES:
1. CE
X
low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CE
X
high is defined at the
first edge of CE0, CE1, or CE2 that disables the device (see
Table 13).
2. When reading the flash array a faster t
GLQV
(R16) applies. For non-array reads, R4 applies (i.e.: Status
Register reads, query reads, or device identifier reads).
Figure 10. 4-Word Page Mode Read Waveform
R1
R2
A[MAX:3] [A]
A[2:1] [A]
R3
CEx [E]
R4
OE# [G]
WE# [W]
R8
R10
R9
2
3
4
00
01
10
11
R6
R7
D[15:0] [Q]
R5
RP# [P]
1
R10
R15
NOTE:
CE
X
low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CE
X
high is defined at
the first edge of CE0, CE1, or CE2 that disables the device (see
Table 13).
24
Datasheet

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