E28F640J3C-150 Datasheet

  • E28F640J3C-150

  • Intel StrataFlash Memory (J3)

  • 909.85KB

  • 72页

  • INTEL   INTEL

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256-Mbit J3 (x8/x16)
9.2
Device Commands
When the V
PEN
voltage
鈮?/div>
V
PENLK
, only read operations from the Status Register, CFI, identifier
codes, or blocks are enabled. Placing V
PENH
on V
PEN
additionally enables block erase, program,
and lock-bit configuration operations. Device operations are selected by writing specific
commands into the CUI.
Table 14, 鈥淐ommand Bus-Cycle Definitions鈥?on page 35
defines these
commands.
Table 14. Command Bus-Cycle Definitions (Sheet 1 of 2)
Command
Scalable or
Basic
Command
Set
(2)
SCS/BCS
SCS/BCS
SCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS
SCS
Bus
Cycles
Req鈥檇.
1
鈮?/div>
2
鈮?/div>
2
2
1
>2
2
2
1
1
2
2
First Bus Cycle
Oper
(3)
Second Bus Cycle
Notes
(5,6)
Addr
X
X
X
X
X
BA
X
BA
X
X
X
X
(4)
Data
Oper
(3)
Addr
(4)
Data
(5,6)
Read Array
Read Identifier Codes
Read Query
Read Status Register
Clear Status Register
Write to Buffer
Word/Byte Program
Block Erase
Block Erase, Program
Suspend
Block Erase, Program
Resume
Configuration
Set Block Lock-Bit
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
0xFF
0X90
0x98
0x70
0x50
0xE8
0x40 or
0x10
0x20
0xB0
0xD0
0xB8
0x60
Write
Write
X
BA
CC
0x01
Write
Write
Write
BA
PA
BA
N
PD
0xD0
Read
Read
Read
IA
QA
X
ID
QD
SRD
1
1,7
1
1,8
1
1,9, 10,
11
1,12,13
1,11,12
1,12,14
1,12
1
1
Datasheet
35

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