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E28F640J3C-150 Datasheet

  • E28F640J3C-150

  • Intel StrataFlash Memory (J3)

  • 909.85KB

  • 72页

  • INTEL   INTEL

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256-Mbit J3 (x8/x16)
10.2
Read Identifier Codes
The Read identifier codes operation outputs the manufacturer code, device-code, and the block
lock configuration codes for each block (See
Section 9.2, 鈥淒evice Commands鈥?on page 35
for
details on issuing the Read Device Identifier command). Page-mode reads are not supported in this
read mode. To terminate the operation, write another valid command. Like the Read Array
command, the Read Identifier Codes command functions independently of the V
PEN
voltage. This
command is valid only when the WSM is off or the device is suspended. Following the Read
Identifier Codes command, the following information can be read.
Table 17. Read Identifier Codes
Code
Manufacture Code
Device Code
32-Mbit
64-Mbit
128-Mbit
256-Mbit
Block Lock Configuration
鈥?/div>
Block Is Unlocked
鈥?/div>
Block Is Locked
鈥?/div>
Reserved for Future Use
Address
(1)
00000
00001
00001
00001
00001
X
0002
(2)
Data
(00) 89
(00) 16
(00) 17
(00) 18
(00) 1D
D0 = 0
D0 = 1
D[7:1]
NOTES:
1. A0 is not used in either x8 or x16 modes when obtaining the identifier
codes. The lowest order address line is A1. Data is always presented
on the low byte in x16 mode (upper byte contains 00h).
2. X selects the specific block鈥檚 lock configuration code.
3. D[7:1] are invalid and should be ignored.
10.2.1
Read Status Register
The Status Register may be read to determine when a block erase, program, or lock-bit
configuration is complete and whether the operation completed successfully. It may be read only
after the specified time W12 (see
Table 9, 鈥淲rite Operations鈥?on page 26).
After writing this
command, all subsequent read operations output data from the Status Register until another valid
command is written. Page-mode reads are not supported in this read mode. The Status Register
contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables
the device (see
Table 13, 鈥淐hip Enable Truth Table鈥?on page 33).
OE# must toggle to V
IH
or the
device must be disabled before further reads to update the Status Register latch. The Read Status
Register command functions independently of the V
PEN
voltage.
During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid
until the Write State Machine completes or suspends the operation. Device I/O signals D[6:0] and
D[15:8] are placed in a high-impedance state. When the operation completes or suspends (check
SR.7), all contents of the Status Register are valid when read.
Datasheet
39

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