您的位置：维库电子市场网 > Datasheet > E28F640J3C-150

E28F640J3C-150 Datasheet

  • E28F640J3C-150

  • Intel StrataFlash Memory (J3)

  • 909.85KB

  • 72页

  • INTEL   INTEL

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

256-Mbit J3 (x8/x16)
13.0
Security Modes
This device offers both hardware and software security features. Block lock operations, PRs, and
VPEN allow the user to implement various levels of data protection. The following section
describes security features in detail.
Other security features are available that are not described in this datasheet. Please contact your
local Intel Field Representative for more information.
13.1
Set Block Lock-Bit
A flexible block locking scheme is enabled via block lock-bits. The block lock-bits gate program
and erase operations. Individual block lock-bits can be set using the Set Block Lock-Bit command.
This command is invalid while the WSM is running or the device is suspended.
Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with
appropriate block address is followed by either the set block lock-bit confirm (and an address
within the block to be locked). The WSM then controls the set lock-bit algorithm. After the
sequence is written, the device automatically outputs Status Register data when read (see
Figure 24
on page 65).
The CPU can detect the completion of the set lock-bit event by analyzing the STS
signal output or SR.7.
When the set lock-bit operation is complete, SR.4 should be checked. If an error is detected, the
Status Register should be cleared. The CUI will remain in Read Status Register mode until a new
command is issued.
This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally
set. An invalid Set Block Lock-Bit command will result in SR.4 and SR.5 being set. Also, reliable
operations occur only when V
CC
and V
PEN
are valid. With V
PEN
鈮?/div>
V
PENLK
, lock-bit contents are
protected against alteration.
13.2
Clear Block Lock-Bits
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lock-
bits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while
the WSM is running or the device is suspended.
Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup
is first written. The device automatically outputs Status Register data when read (see
Figure 25 on
page 66).
The CPU can detect completion of the clear block lock-bits event by analyzing the STS
signal output or SR.7.
When the operation is complete, SR.5 should be checked. If a clear block lock-bit error is detected,
the Status Register should be cleared. The CUI will remain in Read Status Register mode until
another command is issued.
46
Datasheet

E28F640J3C-150相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！