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E28F640J3C-150 Datasheet

  • E28F640J3C-150

  • Intel StrataFlash Memory (J3)

  • 909.85KB

  • 72页

  • INTEL   INTEL

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Contents
Revision History
Date of
Revision
07/07/99
08/03/99
09/07/99
Version
-001
-002
-003
Original Version
A
0
鈥揂
2
indicated on block diagram
Changed Minimum Block Erase time,I
OL
, I
OH
, Page Mode and Byte Mode
currents. Modified RP# on
AC Waveform for Write Operations
Changed Block Erase time and t
AVWH
Removed all references to 5 V I/O operation
Corrected
Ordering Information,
Valid Combinations entries
12/16/99
-004
Changed Min program time to 211 碌s
Added DU to Lead Descriptions table
Changed Chip Scale Package to Ball Grid Array Package
Changed default read mode to page mode
Removed erase queuing from Figure 10,
Block Erase Flowchart
Added Program Max time
Added Erase Max time
Added Max page mode read current
Moved tables to correspond with sections
Fixed typographical errors in ordering information and DC parameter table
Removed V
CCQ1
setting and changed V
CCQ2/3
to V
CCQ1/2
03/16/00
-005
Added recommended resister value for STS pin
Change operation temperature range
Removed note that rp# could go to 14 V
Removed V
OL
of 0.45 V; Removed V
OH
of 2.4 V
Updated I
CCR
Typ values
Added Max lock-bit program and lock times
Added note on max measurements
Updated cover sheet statement of 700 million units to one billion
06/26/00
-006
Corrected Table 10 to show correct maximum program times
Corrected error in Max block program time in section 6.7
Corrected typical erase time in section 6.7
Updated cover page to reflect 100K minimum erase cycles
Updated cover page to reflect 110 ns 32M read speed
Removed Set Read Configuration command from Table 4
Updated Table 8 to reflect reserved bits are 1-7; not 2-7
Updated Table 16 bit 2 definition from R to PSS
2/15/01
-007
Changed V
PENLK
Max voltage from 0.8 V to 2.0 V, Section 6.4,
DC
Characteristics
Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5,
AC Characteristics鈥揜ead-Only Operations
(1,2)
Updated write parameter W13 (t
WHRL
) from 90 ns to 500 ns, Section 6.6,
AC
Characteristics鈥揥rite Operations
Updated Max. Program Suspend Latency W16 (t
WHRH1
) from 30 to 75 碌s,
Section 6.7,
Block Erase, Program, and Lock-Bit Configuration Performance
Description
(1,2,3)
04/13/01
-008
Revised Section 7.0,
Ordering Information
Datasheet
5

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