您的位置：维库电子市场网 > Datasheet > E28F640J3C-150

E28F640J3C-150 Datasheet

  • E28F640J3C-150

  • Intel StrataFlash Memory (J3)

  • 909.85KB

  • 72页

  • INTEL   INTEL

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

256-Mbit J3 (x8/x16)
14.0
Special Modes
This section describes how to read the status, ID, and CFI registers. This section also details how to
configure the STS signal.
14.1
Set Read Configuration Register Command
This command is no longer supported on J3A or J3C. The J3A device will ignore this command,
while the J3C device will
result in an invalid command sequence (SR.4 and SR.5 =1).
14.2
Status (STS)
The Status (STS) signal can be configured to different states using the Configuration command.
Once the STS signal has been configured, it remains in that configuration until another
configuration command is issued or RP# is asserted low. Initially, the STS signal defaults to RY/
BY# operation where RY/BY# low indicates that the WSM is busy. RY/BY# high indicates that the
state machine is ready for a new operation or suspended.
Table 22, 鈥淪TS Configuration Coding
Definitions鈥?on page 50
displays the possible STS configurations.
To reconfigure the Status (STS) signal to other modes, the Configuration command is given
followed by the desired configuration code. The three alternate configurations are all pulse mode
for use as a system interrupt as described below. For these configurations, bit 0 controls Erase
Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 0x00
configuration code with the Configuration command resets the STS signal to the default RY/BY#
level mode. The possible configurations and their usage are described in
Table 22, 鈥淪TS
Configuration Coding Definitions鈥?on page 50.
The Configuration command may only be given
when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration
code will result in both SR.4 and SR.5 being set. When configured in one of the pulse modes, the
STS signal pulses low with a typical pulse width of 250 ns.
Table 22. STS Configuration Coding Definitions
D7
D6
D5
D4
D3
D2
D1
Pulse on
Program
Complete
(1)
Notes
Used to control HOLD to a memory controller to prevent accessing a
flash memory subsystem while any flash device's WSM is busy.
Used to generate a system interrupt pulse when any flash device in
an array has completed a block erase. Helpful for reformatting blocks
after file system free space reclamation or 鈥渃leanup.鈥?/div>
D0
Pulse on
Erase
Complete
(1)
Reserved
D[1:0] = STS Configuration Codes
00 = default, level mode;
device ready indication
01 = pulse on Erase Complete
50
Datasheet

E28F640J3C-150相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！