E28F640J3C-150 Datasheet

  • E28F640J3C-150

  • Intel StrataFlash Memory (J3)

  • 909.85KB

  • 72页

  • INTEL   INTEL

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256-Mbit J3 (x8/x16)
Figure 22. Block Erase Flowchart
Bus
Operation
Write
Issue Single Block Erase
Command 20H, Block
Address
Write (Note 1)
Start
Command
Erase Block
Erase
Confirm
Comments
Data = 20H
Addr = Block Address
Data = D0H
Addr = X
Status register data
With the device enabled,
OE# low updates SR
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read
Standby
Write Confirm D0H
Block Address
1. The Erase Confirm byte must follow Erase Setup.
This device does not support erase queuing. Please see
Application note AP-646 For software erase queuing
compatibility.
Full status check can be done after all erase and write
sequences complete. Write FFH after the last operation to
reset the device to read array mode.
Suspend
Erase Loop
Read
Status Register
No
SR.7 =
0
Suspend Erase
Yes
1
Full Status
Check if Desired
Erase Flash
Block(s) Complete
0606_09
Datasheet
63

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