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E28F640J3C-150 Datasheet

  • E28F640J3C-150

  • Intel StrataFlash Memory (J3)

  • 909.85KB

  • 72页

  • INTEL   INTEL

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256-Mbit J3 (x8/x16)
Figure 24. Set Block Lock-Bit Flowchart
Start
Bus
Operation
Write
Command
Set Block Lock-Bit
Setup
Set Block Lock-Bit
Confirm
Comments
Data = 60H
Addr =Block Address
Data = 01H
Addr = Block Address
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write 60H,
Block Address
Write 01H,
Block Address
Write
Read
Read Status Register
Standby
SR.7 =
1
Full Status
Check if Desired
0
Repeat for subsequent lock-bit operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in read
array mode.
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1
SR.3 =
0
1
SR.4,5 =
0
1
SR.4 =
0
Set Lock-Bit
Successful
Set Lock-Bit Error
Command Sequence
Error
Voltage Range Error
Standby
Bus
Operation
Standby
Command
Comments
Check SR.3
1 = Programming Voltage Error
Detect
Check SR.4, 5
Both 1 = Command Sequence
Error
Check SR.4
1 = Set Lock-Bit Error
Standby
SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register
command, in cases where multiple lock-bits are set before full status is
checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
Datasheet
65

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