鈥?/div>
Six extra instructions for addressing extended program space
Program memory in the device is organized into 128 pages that are each 64K in length.
The value of the XPC register defines the page selection. This register is memory-mapped into data space
to address 001Eh. At a hardware reset, the XPC is initialized to 0.
3.2
On-Chip ROM With Bootloader
The device features a 16K-word
脳
16-bit on-chip maskable ROM that can only be mapped into program
memory space.
Customers can arrange to have the ROM of the device programmed with contents unique to any particular
application.
A bootloader is available in the standard on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If MP/MC of
the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip
ROM. This location contains a branch instruction to the start of the bootloader program.
The standard devices provide different ways to download the code to accommodate various system
requirements:
鈥?/div>
Parallel from 8-bit or 16-bit-wide EPROM
鈥?/div>
Parallel from I/O space, 8-bit or 16-bit mode
鈥?/div>
Serial boot from serial ports, 8-bit or 16-bit mode
鈥?/div>
Host-port interface boot
鈥?/div>
Warm boot
18
Functional Overview
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