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TMS320VC5416GGU160 Datasheet

  • TMS320VC5416GGU160

  • TMS320VC5416 Fixed-Point Digital Signal Processor

  • 855.08KB

  • 98页

  • TI

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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O 鈥?MARCH 1999 鈥?REVISED JANUARY 2005
The standard on-chip ROM layout is shown in Table 3-1.
Table 3-1. Standard On-Chip ROM Layout
ADDRESS RANGE
C000h-D4FFh
D500h-F7FFh
F800h-FBFFh
FC00h-FCFFh
FD00h-FDFFh
FE00h-FEFFh
FF00h-FF7Fh
FF80h-FFFFh
(1)
Reserved
Bootloader
碌-Law expansion table
A-Law expansion table
Sine look-up table
Reserved
(1)
Interrupt vector table
DESCRIPTION
ROM tables for the GSM EFR speech codec
In the ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must
reserve these 128 words at addresses FF00h-FF7Fh in program space.
3.3
On-Chip RAM
The device contains 64K-word
脳
16-bit of on-chip dual-access RAM (DARAM) and 64K-word
脳
16-bit of
on-chip single-access RAM (SARAM).
The DARAM is composed of eight blocks of 8K words each. Each block in the DARAM can support two
reads in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address
range 0080h-7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit
to one. The other four blocks of DARAM are located in the address range 18000h-1FFFFh in program
space. The DARAM located in the address range 18000h-1FFFFh in program space can be mapped into
data space by setting the DROM bit to one.
The SARAM is composed of eight blocks of 8K words each. Each of these eight blocks is a single-access
memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a
data word is written to another SARAM block. The SARAM is located in the address range
28000h-2FFFFh, and 38000h-3FFFFh in program space.
3.4
On-Chip Memory Security
The device has a maskable option to protect the contents of on-chip memories.
When the
RAM/ROM
security option is selected, the following restrictions apply:
鈥?/div>
Only the on-chip ROM originating instructions can read the contents of the on-chip ROM; on-chip RAM
and external RAM originating instruction can not read data from ROM: instead 0FFFFh is read. Code
can still branch to ROM from on-chip RAM or external program memory.
鈥?/div>
The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external
memory. To protect the internal RAM, the user must never branch to external memory.
鈥?/div>
The security feature completely disables the scan-based emulation capability of the 54x to prevent the
use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG
boundary scan test capability.
鈥?/div>
The device is internally forced into microcomputer mode at reset (MP/MC bit forced to zero),
preventing the ROM from being disabled by the external MP/MC pin. The status of the MP/MC bit in
the PMST register can be changed after reset by the user application.
鈥?/div>
HPI writes have no restriction, but HPI reads are restricted to the 4000h - 5FFFh address range.
Functional Overview
19

TMS320VC5416GGU160 产品属性

  • 160

  • 集成电路 (IC)

  • 嵌入式 - DSP（数字式信号处理器）

  • TMS320C54x

  • 定点

  • 主机接口，McBSP

  • 160MHz

  • ROM（32 kB）

  • 256kB

  • 3.30V

  • 1.60V

  • -40°C ~ 100°C

  • 表面贴装

  • 144-LFBGA

  • 144-BGA MICROSTAR（12x12）

  • 托盘

  • 296-15829-ND - DSP STARTER KIT FOR TMS320C5416

  • 296-11660296-11660-5296-11660-5-ND

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