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TMS320VC5416GGU160 Datasheet

  • TMS320VC5416GGU160

  • TMS320VC5416 Fixed-Point Digital Signal Processor

  • 855.08KB

  • 98页

  • TI

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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O 鈥?MARCH 1999 鈥?REVISED JANUARY 2005
www.ti.com
3.17
DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main
control register (DMPREC) is a standard memory-mapped register. However, the other registers are
accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed
through a single memory location. The DMA subbank address (DMSA) register is used as a pointer to
select a particular register within the subbank, while the DMA subbank data (DMSD) register or the DMA
subbank data register with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincremented so that a subsequent access affects the next register within the subbank. This
autoincrement feature is intended for efficient, successive accesses to several control registers. If the
autoincrement feature is not required, the DMSDN register should be used to access the subbank.
Table 3-18 shows the DMA controller subbank addressed registers and their corresponding subaddresses.
Table 3-18. DMA Subbank Addressed Registers
NAME
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
DMDST1
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
DMMCR3
DMSRC4
DMDST4
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
DMSRCP
ADDRESS
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
SUB- AD-
DRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
DESCRIPTION
DMA channel 0 source address register
DMA channel 0 destination address register
DMA channel 0 element count register
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA channel 1 destination address register
DMA channel 1 element count register
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
DMA channel 3 destination address register
DMA channel 3 element count register
DMA channel 3 sync select and frame count register
DMA channel 3 transfer mode control register
DMA channel 4 source address register
DMA channel 4 destination address register
DMA channel 4 element count register
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common channel)
48
Functional Overview

TMS320VC5416GGU160 产品属性

  • 160

  • 集成电路 (IC)

  • 嵌入式 - DSP（数字式信号处理器）

  • TMS320C54x

  • 定点

  • 主机接口，McBSP

  • 160MHz

  • ROM（32 kB）

  • 256kB

  • 3.30V

  • 1.60V

  • -40°C ~ 100°C

  • 表面贴装

  • 144-LFBGA

  • 144-BGA MICROSTAR（12x12）

  • 托盘

  • 296-15829-ND - DSP STARTER KIT FOR TMS320C5416

  • 296-11660296-11660-5296-11660-5-ND

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