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TMS320VC5416GGU160 Datasheet

  • TMS320VC5416GGU160

  • TMS320VC5416 Fixed-Point Digital Signal Processor

  • 855.08KB

  • 98页

  • TI

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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O 鈥?MARCH 1999 鈥?REVISED JANUARY 2005
List of Figures
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
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3-9
3-10
3-11
3-12
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3-15
3-16
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3-18
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3-20
3-21
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3-23
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5-2
5-3
5-4
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5-6
5-7
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5-9
5-10
5-11
5-12
5-13
5-14
144-Ball GGU MicroStar BGA鈩?(Bottom View)
.............................................................................
10
144-Pin PGE Low-Profile Quad Flatpack (Top View)
.......................................................................
12
TMS320VC5416 Functional Block Diagram
..................................................................................
16
Program and Data Memory Map
................................................................................................
20
...............................................................................................
Process Mode Status Register
..................................................................................................
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
.........................
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
.........................
Bank-Switching Control Register BSCR)[MMR Address 0029h]
...........................................................
Host-Port Interface 鈥?Nonmulltiplexed Mode
.................................................................................
HPI Memory Map
.................................................................................................................
Multichannel Control Register (MCR1)
.........................................................................................
Multichannel Control Register (MCR2)
.........................................................................................
Pin Control Register (PCR)
......................................................................................................
Nonconsecutive Memory Read and I/O Read Bus Sequence
.............................................................
Consecutive Memory Read Bus Sequence (n = 3 reads)
..................................................................
Memory Write and I/O Write Bus Sequence
.................................................................................
DMA Transfer Mode Control Register (DMMCRn)
...........................................................................
On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
.........................................
On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
....................................
DMPREC Register
................................................................................................................
General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]
................................................
General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
.................................................
Device ID Register (CSIDR) [MMR Address 003Eh]
.........................................................................
IFR and IMR Registers
...........................................................................................................
Tester Pin Electronics
............................................................................................................
Internal Divide-By-Two Clock Option With External Crystal
...............................................................
External Divide-By-Two Clock Timing
.........................................................................................
Multiply-By-One Clock Timing
..................................................................................................
Nonconsecutive Mode Memory Reads
.......................................................................................
Consecutive Mode Memory Reads
............................................................................................
Memory Write (MSTRB = 0)
....................................................................................................
Parallel I/O Port Read (IOSTRB = 0)
.........................................................................................
Parallel I/O Port Write (IOSTRB = 0)
..........................................................................................
Memory Read With Externally Generated Wait States
.....................................................................
Memory Write With Externally Generated Wait States
.....................................................................
I/O Read With Externally Generated Wait States
...........................................................................
I/O Write With Externally Generated Wait States
...........................................................................
HOLD and HOLDA Timings (HM = 1)
.........................................................................................
Extended Program Memory Map
List of Figures
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5

TMS320VC5416GGU160 产品属性

  • 160

  • 集成电路 (IC)

  • 嵌入式 - DSP（数字式信号处理器）

  • TMS320C54x

  • 定点

  • 主机接口，McBSP

  • 160MHz

  • ROM（32 kB）

  • 256kB

  • 3.30V

  • 1.60V

  • -40°C ~ 100°C

  • 表面贴装

  • 144-LFBGA

  • 144-BGA MICROSTAR（12x12）

  • 托盘

  • 296-15829-ND - DSP STARTER KIT FOR TMS320C5416

  • 296-11660296-11660-5296-11660-5-ND

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