TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O 鈥?MARCH 1999 鈥?REVISED JANUARY 2005
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5.3.3
Internal Oscillator With External Crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is de-
vice-dependent; see Section Section 3.10) and connecting a crystal or ceramic resonator across X1 and
X2/CLKIN. The CPU clock frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The
multiply ratio is determined by the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30
鈩?/div>
maximum and power dissipation of 1 mW. The connection of the required circuit,
consisting of the crystal and two load capacitors, is shown in Figure 5-2. The load capacitors, C
1
and C
2
,
should be chosen such that the equation below is satisfied. C
L
(recommended value of 10 pF) in the
equation is the load specified for the crystal.
C
L
+
C
1
C
2
(C
1
)
C
2
)
Table 5-1. Input Clock Frequency Characteristics
MIN
f
x
(1)
(2)
Input clock frequency
10
(1)
MAX
20
(2)
Unit
MHz
This device utilizes a fully static design and therefore can operate with t
c(CI)
approaching
鈭?
The device is characterized at frequencies
approaching 0 Hz
It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.
X1
Crystal
X2/CLKIN
C1
C2
Figure 5-2. Internal Divide-By-Two Clock Option With External Crystal
56
Electrical Specifications
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