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TMS320VC5416GGU160 Datasheet

  • TMS320VC5416GGU160

  • TMS320VC5416 Fixed-Point Digital Signal Processor

  • 855.08KB

  • 98页

  • TI

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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O 鈥?MARCH 1999 鈥?REVISED JANUARY 2005
List of Tables
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
.........................................
Signal Descriptions
...............................................................................................................
Standard On-Chip ROM Layout
...............................................................................................
Processor Mode Status (PMST) Register Bit Fields
........................................................................
Software Wait-State Register (SWWSR) Bit Fields
.........................................................................
Software Wait-State Control Register (SWCR) Bit Fields
..................................................................
Bank-Switching Control Register (BSCR) Fields
..............................................................................
Bus Holder Control Bits
..........................................................................................................
Sample Rate Input Clock Selection
...........................................................................................
Clock Mode Settings at Reset
.................................................................................................
DMD Section of the DMMCRn Register
......................................................................................
DMA Reload Register Selection
...............................................................................................
DMA Interrupts
...................................................................................................................
DMA Synchronization Events
..................................................................................................
DMA Channel Interrupt Selection
..............................................................................................
Device ID Register (CSIDR) Bits
................................................................................................
CPU Memory-Mapped Registers
................................................................................................
Peripheral Memory-Mapped Registers for Each DSP Subsystem
........................................................
McBSP Control Registers and Subaddresses
.................................................................................
DMA Subbank Addressed Registers
...........................................................................................
Interrupt Locations and Priorities
................................................................................................
Input Clock Frequency Characteristics
.........................................................................................
Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options
.......................................
Divide-By-2 and Divide-By-4 Clock Options Timing Requirements
.......................................................
Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics
...................................................
Multiply-By-N Clock Option Timing Requirements
..........................................................................
Multiply-By-N Clock Option Switching Characteristics
......................................................................
Memory Read Timing Requirements
..........................................................................................
Memory Read Switching Characteristics
.....................................................................................
Memory Write Switching Characteristics
.....................................................................................
I/O Read Timing Requirements
................................................................................................
I/O Read Switching Characteristics
...........................................................................................
I/O Write Switching Characteristics
............................................................................................
Ready Timing Requirements for Externally Generated Wait States
......................................................
Ready Switching Characteristics for Externally Generated Wait States
..................................................
HOLD and HOLDA Timing Requirements
....................................................................................
HOLD and HOLDA Switching Characteristics
...............................................................................
Reset, BIO, Interrupt, and MP/MC Timing Requirements
..................................................................
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
...........................
Terminal Assignments for the TMS320VC5416GGU (144-Pin BGA Package)
List of Tables
11
13
19
22
24
24
25
26
32
33
38
41
42
42
43
45
45
46
47
48
50
56
57
57
57
59
59
60
60
63
64
64
65
67
67
72
72
74
76
7

TMS320VC5416GGU160 产品属性

  • 160

  • 集成电路 (IC)

  • 嵌入式 - DSP（数字式信号处理器）

  • TMS320C54x

  • 定点

  • 主机接口，McBSP

  • 160MHz

  • ROM（32 kB）

  • 256kB

  • 3.30V

  • 1.60V

  • -40°C ~ 100°C

  • 表面贴装

  • 144-LFBGA

  • 144-BGA MICROSTAR（12x12）

  • 托盘

  • 296-15829-ND - DSP STARTER KIT FOR TMS320C5416

  • 296-11660296-11660-5296-11660-5-ND

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