TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O 鈥?MARCH 1999 鈥?REVISED JANUARY 2005
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5.5.6
HOLD and HOLDA Timings
Table 5-15 and Table 5-16 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 5-14).
Table 5-15. HOLD and HOLDA Timing Requirements
5416-120
5416-160
MIN
t
w(HOLD)
t
su(HOLD)
(1)
Pulse duration, HOLD low duration
Setup time, HOLD before CLKOUT low
(1)
4H+8
7
MAX
ns
ns
UNIT
This input can be driven from an asynchronous source, therefore, there are no specific timing requirments with respect to CLKOUT.
However, if this timing is met, the input will be recognized on the CLKOUT edge referenced.
Table 5-16. HOLD and HOLDA Switching Characteristics
5416-120
5416-160
MIN
t
dis(CLKL-A)
t
dis(CLKL-RW)
t
dis(CLKL-S)
t
en(CLKL-A)
t
en(CLKL-RW)
t
en(CLKL-S)
t
v(HOLDA)
t
w(HOLDA)
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, Address, PS, DS, IS valid from CLKOUT low
Enable time, R/W enabled from CLKOUT low
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
Valid time, HOLDA low after CLKOUT low
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2
鈥?
鈥?
2H鈥?
MAX
3
3
3
2H+3
2H+3
2H+3
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
UNIT
72
Electrical Specifications