TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O 鈥?MARCH 1999 鈥?REVISED JANUARY 2005
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5.5.8
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 5-18 assumes testing over recommended operating conditions and H = 0.5t
c(CO)
(see Figure 5-18).
Table 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
5416-120
5416-160
MIN
t
d(CLKL-IAQL)
t
d(CLKL-IAQH)
t
d(CLKL-IACKL)
t
d(CLKL-IACKH)
t
d(CLKL-A)
t
w(IAQL)
t
w(IACKL)
Delay time, CLKOUT low to IAQ low
Delay time, CLKOUT low to IAQ high
Delay time, CLKOUT low to IACK low
Delay time, CLKOUT low to IACK high
Delay time, CLKOUT low to address valid
Pulse duration, IAQ low
Pulse duration, IACK low
鈥?
鈥?
鈥?
鈥?
鈥?
2H 鈥?2
2H 鈥?2
MAX
4
4
4
4
4
ns
ns
ns
ns
ns
ns
ns
PARAMETER
UNIT
CLKOUT
t
d(CLKL鈭扐)
t
d(CLKL鈭扐)
A[22:0]
t
d(CLKL 鈭?IAQL)
t
d(CLKL 鈭?IAQH)
IAQ
t
w(IAQL)
t
d(CLKL 鈭?IACKL)
t
d(CLKL 鈭?IACKH)
t
w(IACKL)
IACK
Figure 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
76
Electrical Specifications