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TMS320VC5416GGU160 Datasheet

  • TMS320VC5416GGU160

  • TMS320VC5416 Fixed-Point Digital Signal Processor

  • 855.08KB

  • 98页

  • TI

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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O 鈥?MARCH 1999 鈥?REVISED JANUARY 2005
www.ti.com
5.5.10.3
McBSP as SPI Master or Slave Timing
Table 5-24 to Table 5-31 assume testing over recommended operating conditions (see Figure 5-24,
Figure 5-25, Figure 5-26, and Figure 5-27).
Table 5-24. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
(1)
5416-120
5416-160
MASTER
MIN
t
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
(1)
(2)
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
12
4
MAX
5+
SLAVE
MIN
2 鈥?6P
(2)
12P
(2)
MAX
ns
ns
UNIT
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock.
Table 5-25. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
(1)
5416-120
5416-160
PARAMETER
MASTER
(2)
MIN
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
d(BCKXH-BDXV)
t
dis(BCKXL-BDXHZ)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
(1)
(2)
(3)
Hold time, BFSX low after BCLKX low
(3)
Delay time, BFSX low to BCLKX high
(4)
Delay time, BCLKX high to BDX valid
Disable time, BDX high impedance following last data bit from
BCLKX low
Disable time, BDX high impedance following last data bit from
BFSX high
Delay time, BFSX low to BDX valid
T鈥?
C鈥?
鈥?
C鈥?
MAX
T+4
C+3
5
C+3
2P鈥?4
(5)
4P+ 2
(5)
6P + 17
(5)
8P + 17
(5)
6P + 2
(5)
10P + 17
(5)
SLAVE
MIN
MAX
ns
ns
ns
ns
ns
ns
UNIT
(4)
(5)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) *2P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP
CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the
master clock (BCLKX).
P = 0.5 * processor clock.
LSB
MSB
BCLKX
t
h(BCKXL-BFXL)
BFSX
t
dis(BFXH-BDXHZ)
t
dis(BCKXL-BDXHZ)
BDX
Bit 0
t
su(BDRV-BCLXL)
BDR
Bit 0
Bit(n-1)
Bit(n-1)
t
d(BFXL-BDXV)
t
d(BCKXH-BDXV)
(n-2)
t
h(BCKXL-BDRV)
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
t
d(BFXL-BCKXH)
Figure 5-24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
82
Electrical Specifications

TMS320VC5416GGU160 产品属性

  • 160

  • 集成电路 (IC)

  • 嵌入式 - DSP（数字式信号处理器）

  • TMS320C54x

  • 定点

  • 主机接口，McBSP

  • 160MHz

  • ROM（32 kB）

  • 256kB

  • 3.30V

  • 1.60V

  • -40°C ~ 100°C

  • 表面贴装

  • 144-LFBGA

  • 144-BGA MICROSTAR（12x12）

  • 托盘

  • 296-15829-ND - DSP STARTER KIT FOR TMS320C5416

  • 296-11660296-11660-5296-11660-5-ND

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