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CR16MCS5VJI8 Datasheet

  • CR16MCS5VJI8

  • Family of 16-bit CAN-enabled CompactRISC Microcontrollers

  • 713.21KB

  • 156页

  • NSC

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5.0
System Configuration
CLK1OE
normal operating mode, the CLK pin operates
as a CPU clock output.
Generated Clock Output 1 Enable. When
cleared (0), the CLKOUT1 pin (ENV0) stays in
high impedance state. When set (1), the pin
outputs the clock from the prescaler controlled
by PRSSC1.SCDIV1.
Generated Clock Output 2 Enable. When this
bit is set (1) and CLKOE is cleared, the
CLKOUT2 pin (ENV1) outputs the clock from
the prescaler controlled by PRSSC1.SCDIV2.
Otherwise, the CLKOUT2 pin is in high imped-
ance state.
The device has two input pins, ENV0 and ENV1, which are
used to specify the operating environment of the device upon
reset. There are also two system configuration registers,
called the Module Configuration (MCFG) register and the
Module Status (MSTAT) register.
5.1
ENV0 AND ENV1 PINS
CLK2OE
Upon reset, the operating mode of the device is determined
by the state of the ENV0 and ENV1 input pins, as indicated
in Table6.
Table 6 Operating Environment Selection
ENV1
0
0
1
1
ENV0
0
1
0
1
Operating Environment
Test Mode Flash Memory
Test Mode
In-System-Programming mode (ISP)
Internal ROM enabled Mode (IRE), if
program memory is not empty; or ISP-
Mode, if program memory is empty
5.3
MODULE STATUS (MSTAT) REGISTER
The MSTAT register is a byte-wide, read-only register that in-
dicates the general status of the device.
The MCFG register format is shown below.
7
4
Reserved
OENV(1:0)
3
PGMBUSY
2
Reserved
1
OENV1
0
OENV0
In the case where the ENV1 and ENV0 pins are both high,
the reset algorithm looks at the FLCTRL2.EMPTY bit to de-
termine whether the program memory is empty, and sets the
operating mode accordingly.
The ENV0 and ENV1 pins have on-chip pull-up devices that
are enabled during reset while the pins are being sampled.
Therefore, if they are left unconnected, the inputs are consid-
ered high and the normal operating mode (IRE-Mode) is se-
lected and the CPU starts to execute code at address 0. To
enter any other operating mode, the external hardware must
drive the appropriate input low.
In the case where the ISP-Mode is selected, the chip starts
executing the ISP code residing in the on-chip ISP-Memory
area.
The test modes are Reserved for factory testing and for ex-
ternal programming of the flash EEPROM program memory.
They should not be invoked otherwise.
Operating Environment. These two bits contain
the values applied to the ENV1 and ENV0 pins
upon reset. These bit values are controlled by
the external hardware upon reset and are held
constant in the register until the next reset.
PGMBUSY Flash EEPROM Programming Busy. This bit is
automatically set to 1 when either the program
memory or the data memory is busy being pro-
grammed or erased. It is cleared to 0 when nei-
ther of the two flash EEPROM memories is
busy being programmed or erased. When this
bit is set, the software should not attempt any
write access to either of these two memories.
5.2
MODULE CONFIGURATION (MCFG)
REGISTER
The MCFG register is a byte-wide, read/write register that
sets the clock output features of the device.
Upon reset, the non-reserved bits of this register are cleared
to zero. The start-up software must write a specific value to
this register in order to configure the CLK output pin function.
When the software writes to this register, it must write a zero
to each reserved bit for the device to operate properly. The
register should be written in active mode only, not in power
save, HALT, or IDLE mode. However, the register contents
are preserved during all power modes.
The MCFG register format is shown below.
7
6
5
4
Reserved
3
2
CLK1OE
1
CLKOE
0
Reserved
Reserved CLK2OE
CLKOE
CPU Clock Output Enable. When this bit is
cleared (0), the CLK pin (ENV1) remains in the
high-impedance state. When this bit is set (1) in
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