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CR16MCS5VJI8 Datasheet

  • CR16MCS5VJI8

  • Family of 16-bit CAN-enabled CompactRISC Microcontrollers

  • 713.21KB

  • 156页

  • NSC

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program the prescaler value in advance and leave it un-
changed while a program or erase operation is in progress.
A similar (but separate) prescaler factor is applied to the EE-
PROM data memory. See Section9.1.7 and Section9.3.4 for
details.
9.1.6
Flash EEPROM Program Memory Control and
Status Register (FLCSR)
12.5 MHz / (62+1) = 198.4 kHz. Do not modify this register
while a flash EEPROM program or erase operation is in
progress.
Upon reset, this register is programmed by default with the
value 63 hex (99 decimal), which is an appropriate setting for
a 20 MHz system clock.
9.1.8
Program Memory Start Time Reload (FLSTART)
The Flash EEPROM Program Memory Control and Status
(FLCSR) register is a byte-wide, read/write register that con-
tains several status and control bits related to the program
memory. All reserved bits must be written with 0 for the mem-
ory to operate properly when writing to this register. Upon re-
set, this register is cleared to zero when the flash memory on
the chip is in the idle state.
The register format is shown below.
7
MERASE
6
Reserved
4
3
PMLFULL
2
PMBUSY
1
PMER
0
Reserved
The FLSTART register is a byte-wide read/write register that
controls the program and erase start delay time. This value
is loaded into the lower 8 bits of the flash timing counter, and
at the same time, 00
2
is loaded into the upper 2 bits. Before
you program or erase the program memory for the first time,
program the FLSTART register with the proper prescaler val-
ue, FTSTART. The flash timing counter generates a delay of
(FTSTART+1) prescaler output clocks. The default value
provides a delay time of 10
碌s
when the prescaler output
clock is 200kHz. Do not modify this register while a program
or erase operation is in progress.
Upon reset, this register resets to 01
16
when the flash mem-
ory on the chip is in an idle state.
9.1.9
Program Memory Transition Time Reload
Register (FLTRAN)
PMER
PMBUSY
PMLFULL
MERASE
Flash EEPROM Program Memory page erase.
When set (1) with MERASE bit cleared, a valid
write to the flash EEPROM program memory
erases the entire flash EEPROM program
memory page pointed to by the write address
rather than performing a write to the addressed
memory location.
Program Memory Busy. This bit is automatical-
ly set to 1 when the flash EEPROM program
memory is busy being programmed, and
cleared to 0 at all other times. (The MSTAT.PG-
MBUSY is also set to 1 whenever the PMBUSY
bit is set to 1.)
Program Memory Write-Latch Buffer Full.
When set (1), the double-buffered data register
for program memory write operations is full.
When cleared (0), the double-buffered data
register is not full.
Mass Erase Flash EEPROM Program Memory
Array. When set (1) in ISP or test mode, a valid
write to the flash EEPROM program memory
performs an erase to the whole flash EEPROM
program memory rather than perform a write to
the addressed memory location. However, it is
necessary to enter new values into the
FLERASE and FLEND registers to adjust the
mass erase timing before starting the mass
erase.
The FLTRAN register is a byte-wide read/write register that
controls some program/erase transition times. This value is
loaded into the lower 8 bits of the flash timing counter, and at
the same time, 00
2
is loaded into the upper 2 bits. Before you
program or erase the program memory for the first time, you
should program the FLTRAM register with the proper pres-
caler value, FTTRAN. The flash timing counter generates a
delay of (FTTRAN + 1) prescaler output clocks. The default
value provides a delay time of 5碌s when the prescaler output
clock is 200kHz. Do not modify this register while a program
or erase operation is in progress.
Upon reset, this register resets to 00
1 6
when the flash mem-
ory on the chip is in an idle state.
9.1.10
Program Memory Programming Time Reload
Register (FLPROG)
9.1.7
Program Memory Timing Prescaler Register
(FLPSLR)
The FLPSLR register is a byte-wide, read/write register that
selects the prescaler divider ratio for the flash EEPROM pro-
gram memory programming clock. Before you program or
erase the program memory for the first time, you should pro-
gram the FLPSLR register with the proper prescaler value,
an 8-bit value called FTDIV. The device divides the system
clock by (FTDIV+1) to produce the program memory pro-
gramming clock.
You should choose a value of FTDIV to produce a clock of the
highest possible frequency that is equal to or just less than
200 kHz. For example, if the system clock frequency is 12.5
MHz, use the value 3E hex (62 decimal) for FTDIV, because
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The FLPROG register is a byte-wide read/write register that
controls the programming pulse width. This value is loaded
into the lower 8 bits of the flash timing counter, and at the
same time, 00
2
is loaded into the upper 2 bits. Before you
program or erase the program memory for the first time, pro-
gram the FLPROG register with the proper prescaler value,
FTPROG. The flash timing counter generates a programming
pulse width of (FTPROG + 1) prescaler output clocks. The
default value provides a delay time of 30碌s when the prescal-
er output clock is 200kHz.
Do not modify this register while program/erase operation is
in progress.
Upon reset, this register resets to 05
1 6
when the flash mem-
ory on the chip is in idle state.
24

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