12.0 Dual Clock and Reset
The Dual Clock and Reset module (CLK2RES) generates a
high-speed main system clock from an external crystal net-
work and a slow clock (32.768 kHz or other rate) for operat-
ing the device in Power Save mode. It also provides the main
system reset signal, a power-on reset function, a main clock
prescaler to generate two additional low speed clocks, and
an 32kHz oscillator start-up delay.
Figure7 is block diagram of the Dual Clock and Reset mod-
ule.
Reset
Power-On-Reset
System
Reset
Stop Main Osc.
Preset
X1CKI
Start-Up-Delay
14-Bit Timer
X1CKO
Main Osc.
4-Bit
Prescaler
4-Bit
Prescaler
Div.
by-2
X2CKI
32kHz Osc.
8-Bit
Prescaler
Stop
Main Osc In
Time-out
Good Main
Clk
Main Clk
2 Low
Speed Clk
Outputs
Low Speed
Clk
Mux
Start-Up-Delay
6-Bit Timer
X2CKO
Preset
Time-out
Good Low
Speed Clk
Stop 32kHz Osc.
Figure 7.
Dual Clock and Reset Module Block Diagram
Stop Low
Speed Clk
12.1
EXTERNAL CRYSTAL NETWORK
An external crystal network is required at pins X1CKI and
X1CKO for the main clock. A similar external crystal network
may be used at pins X2CKI and X2CKO for the slow clock in
packages that have these pins. If an external crystal network
is not used for the slow clock, the clock is generated by divid-
ing the fast main clock.
The crystal oscillator you choose may require external com-
ponents different from the ones specified above. In that case,
consult with National鈥檚 engineer for the component specifica-
tions
The crystals and other oscillator components should be
placed close to the X1CKI/X1CLO and X2CKI/X2CLO device
input pins to keep the printed trace lengths to an absolute
minimum.
Figure8 shows the required crystal network at X1CKI/
X1CKO and optional crystal network at X2CKI/X2CKO.
Table13 shows the component specifications for the main
crystal network and Table14 shows the component specifi-
cations for the 32.768 kHz crystal network.
39
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