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CR16MCS5VJI8 Datasheet

  • CR16MCS5VJI8

  • Family of 16-bit CAN-enabled CompactRISC Microcontrollers

  • 713.21KB

  • 156页

  • NSC

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Peripheral Bus
15
..........
WKENA
0
WKICTL1-2
WUI0
0
4
EXINT3:0 to ICU
Wake-Up Signal
To Power Mgt
WUI15
15
WKEDG
WKPND
Figure 9. Multi-Input Wake-Up Module Block Diagram
The register format is shown below.
15
WKEN15-WKEN0
0
00
01
10
11
quests outputs to the ICU31L are to be activat-
ed for the corresponding channel.
enables MIWU Interrupt Request 0
enables MIWU Interrupt Request 1
enables MIWU Interrupt Request 2
enables MIWU Interrupt Request 3
13.3
WAKE-UP INTERRUPT CONTROL
REGISTER 1 (WKCTL1)
The Wake-Up Interrupt Control Register 1 (WKICTL1) regis-
ter is a word-wide read/write register that selects the interrupt
request signal for the associated channels WUI0 to WUI7.
Upon reset, WKICTL1 is set to 0, which selects MIWU Inter-
rupt Request 0 for all eight channels. The register format is
shown below.
15
14 13
12 11
10
9
8
7
6
5
4 3
2
1
0
WKINTR WKINTR WKINTR WKINTR WKINTR WKINTR
7
6
5
4
3
2
WKINTR
1
WKINTR
0
13.5
WAKE-UP PENDING REGISTER (WKPND)
WKINTR0:7 Wake-Up Interrupt Request Select. Each field
selects which of the following four interrupt re-
quests outputs to the ICU31L are to be activat-
ed for the corresponding channel.
00
01
10
11
enables MIWU Interrupt Request 0
enables MIWU Interrupt Request 1
enables MIWU Interrupt Request 2
enables MIWU Interrupt Request 3
The Wake-Up Pending (WKPND) register is a word-wide
read/write register in which the Multi-Input Wake-Up module
latches any detected trigger conditions. Register bits 0
through 15 serve as latches for channels WUI0 through
WUI15, respectively. A bit cleared to 0 indicates that no trig-
ger condition has occurred. A bit set to 1 indicates that a trig-
ger condition has occurred and is pending on the
corresponding channel. This register is cleared upon reset.
The CPU can only write a 1 to any bit position in this register.
If the CPU attempts to write a 0, it has no effect on that bit.
To clear a bit in this register, the CPU must use the WKPCL
register (described below). This implementation prevents a
potential hardware-software conflict during a read-modify-
write operation on the WKPND register.
The register format is shown below.
15
WKPD15-WKPD0
0
13.4
WAKE-UP INTERRUPT CONTROL
REGISTER 1 (WKCTL2)
13.6
The Wake-Up Interrupt Control Register 2 (WKICTL2) regis-
ter is a word-wide read/write register that selects the interrupt
request signal for the associated channels WUI8 to WUI15.
Upon reset, WKICTL2 is set to 0, which selects MIWU Inter-
rupt Request 0 for all eight channels. The register format is
shown below.
15
14 13
12 11
10
9
8
7
6
5
4 3
2
1
0
WKINTR WKINTR WKINTR WKINTR WKINTR WKINTR
15
14
13
12
11
10
WKINTR
9
WKINTR
8
WAKE-UP PENDING CLEAR REGISTER
(WKPCL)
The Wake-Up Pending Clear (WKPCL) register is a word-
wide write-only register that lets the CPU clear bits in the WK-
PND register. Writing a 1 to a bit position in the WKPCL reg-
ister clears the corresponding bit in the WKPND register.
Writing a 0 leaves the corresponding bit in the WKPND reg-
ister unchanged.
Reading this register location returns unknown data. There-
fore, do not use a read-modify-write sequence to set the in-
dividual bits. In other words, do not attempt to read the
WKINTR8:5 Wake-Up Interrupt Request Select. Each field
selects which of the following four interrupt re-
43
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