鈥?/div>
A flexible interrupt scheme with
鈥?four separate system level interrupt requests
鈥?a total of 16 interrupt sources each with a separate in-
terrupt pending flag and interrupt enable bit
16.1
VTU FUNCTIONAL DESCRIPTION
The Versatile-Timer-Unit (VTU) is comprised of four timer
subsystems. Each timer subsystem contains an 8-bit clock
prescaler, a 16-bit up-counter and two 16-bit registers. Each
timer subsystem controls two I/O pins which either function
as PWM outputs or capture inputs depending on the mode of
operation. There are four system level interrupt requests,
one for each timer subsystem. Each system level interrupt re-
quest is controlled by four interrupt pending flags with asso-
ciated enable/disable bits. All four timer subsystems are fully
independent and each may operate as a dual 8-bit PWM tim-
er, a 16-bit PWM timer or as a dual 16-bit capture timer. Fig-
ure 18 illustrates the main elements of the Versatile-Timer-
Unit (VTU).
0
15
MODE
15
0
15
0
15
0
IO1CTL
15
INTCTL
0
IO2CTL
INTPND
Timer Subsystem 1
7
0
7
Timer Subsystem 2
0
7
Timer Subsystem 3
0
7
Timer Subsystem 4
0
C1PRSC
==
Prescaler
Counter
15
0
15
C2PRSC
==
Prescaler
Counter
0
15
C3PRSC
==
Prescaler
Counter
0
15
C4PRSC
==
Prescaler
Counter
0
COUNT1
compare - capture
COUNT2
compare - capture
COUNT3
compare - capture
COUNT4
compare - capture
PERCAP1
compare - capture
PERCAP2
compare - capture
PERCAP3
compare - capture
PERCAP4
compare - capture
DTYCAP1
DTYCAP2
DTYCAP3
DTYCAP4
I/O control
I/O control
I/O control
I/O control
I/O control
I/O control
I/O control
I/O control
TIO1
TIO2
TIO3
TIO4
TIO5
TIO6
TIO7
TIO8
Figure 18. VTU Block Diagram
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