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CR16MCS5VJI8 Datasheet

  • CR16MCS5VJI8

  • Family of 16-bit CAN-enabled CompactRISC Microcontrollers

  • 713.21KB

  • 156页

  • NSC

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refers to timer subsystem 1 but equally applies to the other
three timer subsystems.
7
0
ed with them. All interrupt pending flags are denoted IxAPD
through IxDPD where 鈥渪鈥?relates to the specific timer sub-
system. There is one system level interrupt request for each
of the four timer subsystems.
Figure23 illustrates the interrupt structure of the versatile
timer module.
C1PRSC
==
Prescaler
Counter
T1RUN
15
TMOD1=11
I1AEN
0
[15:0]
I1BEN
I1CEN
I1DEN
System
Interrupt
Request 1
Restart
COUNT1[15:0]
capture
PERCAP1[15:0]
capture
I1APD
I1BPD
I1CPD
DTYCAP1[15:0]
cap
rst
2
0
cap
rst
I1DPD
2
0
C1EDG
TIO1
C2EDG
TIO2
I4AEN
I4BEN
Figure 22. VTU Dual 16-bit Capture Mode
16.1.4
Low Power Mode
I4APD
I4BPD
I4CPD
I4DPD
I4CEN
I4DEN
System
Interrupt
Request 4
In case a timer subsystem is not used, the user can place it
in a low-power-mode. All clocks to a timer subsystem are
stopped and the counter and prescaler contents are frozen
once low-power-mode is entered. The user may continue to
write to the MODE, INTCTL, IOxCTL and CLKxPS registers.
Write operations to the INTPND register are allowed; but if a
timer subsystem is in low power mode, its associated inter-
rupt pending bits cannot be cleared. The user cannot write to
the COUNTx, PERCAPx and DTYCAPx registers of a timer
subsystem while it is in low-power-mode. All registers can be
read at any time.
16.1.5
Interrupts
Figure 23. VTU Interrupt Request Structure
Each of the timer pending flags - IxAPD through IxDPD - is
set by a specific hardware event depending on the mode of
operation, i.e., PWM or Capture mode. Table17 outlines the
specific hardware events relative to the operation mode
which cause an interrupt pending flag to be set.
The Versatile-Timer-Unit (VTU) has a total of 16 interrupt
sources, four for each of the four timer subsystems. All inter-
rupt sources have a pending flag and an enable bit associat-
Table 17
Pending Flag
IxAPD
IxBPD
IxCPD
IxDPD
16.1.6
Dual 8-bit PWM Mode
Low Byte Duty Cycle match
Low Byte Period match
High Byte Duty Cycle match
High Byte Period match
ISE Mode operation
VTU Interrupt Sources
16-bit PWM Mode
Duty Cycle match
Period match
N/A
N/A
Capture Mode
Capture to DTYCAPx
Capture to PERCAPx
Counter Overflow
N/A
16.2
VTU REGISTERS
The VTU supports breakpoint operation of the In-System-
Emulator (ISE). If FREEZE is asserted, all timer counter
clocks will be inhibited and the current value of the timer reg-
isters will be frozen; in capture mode, all further capture
events are disabled. Once FREEZE becomes inactive,
counting will resume from the previous value and the capture
input events are re-enabled.
The Versatile-Timer-Unit contains a total of 19 user accessi-
ble registers. All registers are word-wide and are initialized to
a known value upon reset. All software accesses to the VTU
registers must be word accesses.
61
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