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CR16MCS5VJI8 Datasheet

  • CR16MCS5VJI8

  • Family of 16-bit CAN-enabled CompactRISC Microcontrollers

  • 713.21KB

  • 156页

  • NSC

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16.2.1
Mode Control Register (MODE)
The Mode Control (MODE) registries a word-wide read/write
register which controls the mode selection of all four timer
subsystems. The register is cleared (0000
1 6
) upon reset.
15
14
13
T8RUN
5
T4RUN
12
T7RUN
4
T3RUN
11
10
9
T6RUN
1
T2RUN
8
T5RUN
0
T1RUN
TMOD4
7
6
TMOD3
3
2
value of this three bit field has no effect while
operating in PWM mode.
CxEDG
000
001
010
011
100
101
110
111
PxPOL
Capture
rising edge
falling edge
rising edge
falling edge
both edges
both edges
both edges
both edges
Counter Reset
No
No
Yes
Yes
No
rising edge
falling edge
both edges
TMOD2
TMOD1
TxRUN
TMODx
Timer start/stop. If set (1), the associated
counter and clock prescaler is started depend-
ing on the mode of operation. Once set, the
clock to the clock prescaler and the counter are
enabled and the counter will increment each
time the clock prescaler counter value matches
the value defined in the associated clock pres-
caler field (CxPRSC).
Timer System Operating Mode. This 2-bit wide
field enables or disables the Timer Subsystem
and defines it鈥檚 operating mode.
00:
Low-Power-Mode enabled. All clocks to
the counter subsystem are stopped. The
counter is stopped regardless of the val-
ue of the TxRUN bits. Read operations
to the Timer Subsystem will return the
last value; the user shall not perform any
write operations to the Timer Subsystem
while it is disabled since those will be ig-
nored.
Dual 8-bit PWM mode enabled. Each 8-
bit counter may individually be started or
stopped via its associated TxRUN bit.
The TIOx pins will function as PWM out-
puts.
16-bit PWM mode enabled. The two 8-
bit counters are concatenated to form a
single 16-bit counter. The counter may
be started or stopped with the lower of
the two TxRUN bits, i.e. T1RUN,
T3RUN, T5RUN and T7RUN. The TIOx
pins will function as PWM outputs.
Capture Mode enabled. Both 8-bit
counters are concatenated and operate
as a single 16-bit counter. The counter
may be started or stopped with the lower
of the two TxRUN bits, i.e., T1RUN,
T3RUN, T5RUN and T7RUN. The TIOx
pins will function as capture inputs.
PWM Polarity. While operating in PWM mode
the bit defines the output polarity of the corre-
sponding PWM output (TIOx).
0=
The PWM output is set (1) upon the 00
16
to 01
1 6
transition of the counter and will
be reset (0) once the counter value
matches the duty cycle value.
The PWM output is reset (0) upon the
00
1 6
to 01
16
transition of the counter and
will be set (1) once the counter value
matches the duty cycle value.
1=
01:
Once a counter is stopped, the output will assume the value
of PxPOL, i.e., its initial value. The PxPOL bit has no effect
while operating in capture mode.
16.2.3
I/O Control Register 2 (IO2CTL)
10:
The I/O Control Register 2 (IO2CTL) is a word-wide read/
write register. The register controls the functionality of the
I/O pins TIO5 through TIO8 depending on the selected mode
of operation. The register is cleared (0000) upon reset.
15
14
12
11
10
8
7
6
4
3
2
0
P8POL C8EDG P7POL C7EDG P6POL C6EDG P5POL C5EDG
The functionality of the bit fields of the IO2CTL register is
identical to the ones described in the IO1CTL register sec-
tion.
16.2.4
Interrupt Control Register (INTCTL)
11:
16.2.2
I/O Control Register 1 (IO1CTL)
The Interrupt Control (INTCTL) register is a word-wide read/
write register. It contains the interrupt enable bits for all 16 in-
terrupt sources of the Versatile-Timer-Unit. Each interrupt en-
able bit corresponds to an interrupt pending flag located in
the Interrupt Pending Register (INTPND). All INTCTL regis-
ter bits are solely under software control. The register is
cleared (0000
1 6
) upon reset..
15
14
13
12
11
10
9
8
I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN
The I/O Control Register 1 (IO1CTL) is a word-wide read/
write register. The register controls the functionality of the
I/O pins TIO1 through TIO4 depending on the selected mode
of operation. The register is cleared (0000
1 6
) upon reset.
15
P4POL
14
12
11
10
8
7
6
4
3
2
0
C4EDG P3POL
C3EDG P2POL
C2EDG P1POL
C1EDG
7
6
5
4
3
2
1
0
I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN
IxAEN
CxEDG
Capture Edge Control. Defines the polarity of a
capture event and the reset of the counter. The
Timer x interrupt A enable. Enable/Disable an
interrupt request based on the corresponding
IxAPD flag being set. The associated IxAPD
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