您的位置：维库电子市场网 > Datasheet > CR16MCS5VJI8

CR16MCS5VJI8 Datasheet

  • CR16MCS5VJI8

  • Family of 16-bit CAN-enabled CompactRISC Microcontrollers

  • 713.21KB

  • 156页

  • NSC

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

Interrupt Request
Control + Status
MCS
Read Data
16-bit Read Buffer
Write Data
8
8
MWDAT
Slave
16-bit Shift Register
Data Out
Master
MDODI
Data In
Slave
Master
MDIDO
MSK
MSK
Clock Prescaler + Select
System Clock
Master
Figure 25. MICROWIRE Block Diagram
buffer consists of the 16-bit shifter and a buffer, called the
read buffer.
The 16-bit shifter loads the read buffer with new data when
the data transfer sequence is completed and previous data in
the read buffer has been read. In master mode, an Overrun
error occurs when the read buffer is full, the 16-bit shifter is
full and a new data transfer sequence starts.
When 8-bit mode is selected, the lower byte of the shift reg-
ister is loaded into the lower byte of the read buffer and the
read buffer鈥檚 higher byte remains unchanged.
The 鈥淩eceive Buffer Full鈥?(MRBF) bit indicates if the MWDAT
register holds valid data. The MOVR bit indicates that an
overrun condition has occurred.
17.1.3
Writing
(master mode) or the MDODI pin (slave mode), is sampled
on the rising edge of MSK.
In the alternate mode, the output data is shifted out on the ris-
ing edge of MSK on the MDODI pin (master mode) or MDIDO
pin (slave mode). The input data, which is received via MDI-
DO pin (master mode) or MDODI pin (slave mode), is sam-
pled on the falling edge of MSK.
The clocking modes are selected with the MSKM bit. The
MIDL bit allows selection of the value of MSK when it is idle
(when there is no data being transferred). Various MSK clock
frequencies can be programmed via the MCDV bits. Figures
27, 28, 29, and 30 show the data transfer timing for the nor-
mal and the alternate modes with the MIDL bit equal to 0 and
equal to 1.
Note that when data is shifted out on MDODI (master mode)
or MDIDO (slave mode) on the leading edge of the MSK
clock, bit 14 (16-bit mode) is shifted out on the second lead-
ing edge of the MSK clock. When data are shifted out on
MDODI (master mode) or MDIDO (slave mode) on the trail-
ing edge of MSK, bit 14 (16-bit mode) is shifted out on the first
trailing edge of MSK.
The 鈥淢ICROWIRE Busy鈥?(MBSY) bit indicates whether the
MWDAT register can be written. All write operations to the
MWDAT register update the shifter while the data contained in
the read buffer is not affected. Undefined results will occur if
the MWDAT register is written to while the MBSY bit is set to 1.
17.1.4
Clocking Modes
Two clocking modes are supported: the normal mode and the
alternate mode.
In the normal mode, the output data, which is transmitted on
the MDODI pin (master mode) or the MDIDO pin (slave
mode), is clocked out on the falling edge of the shift clock
MSK. The input data, which is received via the MDIDO pin
17.2
MASTER MODE
In Master mode, the MSK pin is an output for the shift clock,
MSK. When data is written to the (MWnDAT register), eight
or sixteen MSK clocks, depending on the mode selected, are
generated to shift the eight or sixteen bits of data and then
www.national.com
66

CR16MCS5VJI8相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！