UnETI
UnERI
UnEEI
Enable Transmitter Interrupt. This read/write
bit, when set to 1, enables generation of an in-
terrupt when the hardware sets the UnTBE bit.
Enable Receiver Interrupt. This read/write bit,
when set to 1, enables generation of an inter-
rupt when the hardware sets the UnRBF bit.
Enable Receive Error Interrupt. This read/write
bit, when set to 1, enables generation of an in-
terrupt when the hardware sets the UnERR bit
in the UnSTAT register.
System
Clock
20 MHz
18.4.2
Desired
Baud Rate
19200
N
P
Actual
Baud Rate
19230.769
Percent
Error
0.16
5 13
Baud Rate in Synchronous Mode
The equation for calculating the baud rate in synchronous
mode is:
SYS_CLK
BR
= ----------------------------
(
2
脳
N
脳
P
)
where BR is the baud rate, SYS_CLK is the system clock, N
is the value of the baud rate divisor + 1, and P is the prescaler
divide factor selected by the value in the UnPSR register.
Use the same procedure to determine the values of N and P
as in the asynchronous mode. In this case, however, only in-
teger prescaler values are allowed.
18.4
BAUD RATE CALCULATIONS
The USART baud rate is determined by the system clock fre-
quency and the values programmed into the UnPSR and Un-
BAUD registers. Unless the system clock frequency is an
exact multiple of the desired baud rate, there will be a small
amount of error in the resulting baud rate clock.
The method of baud rate calculation depends on whether the
USART is configured to operate in the asynchronous or syn-
chronous mode.
18.4.1
Baud Rate in Asynchronous Mode
The equation for calculating the baud rate in asynchronous
mode is:
SYS_CLK
BR
= -------------------------------
(
16
脳
N
脳
P
)
where BR is the baud rate, SYS_CLK is the system clock, N
is the value of the baud rate divisor + 1, and P is the prescaler
divide factor selected by the value in the UnPSR register.
Assuming a system clock of 5 MHz and a desired baud rate
of 9600, the NxP term according to the equation above is:
(
5
脳10
6
)
N
脳
P
= ----------------------------- = 32.552
(
16
脳
9600
)
The NxP term is then divided by each Prescaler Factor from
Table 19 to obtain a value closest to an integer. The factor for
this example is 6.5.
32.552
N
= ---------------- = 5.008 (N = 5)
6.5
The baud rate register is programmed with a baud rate divi-
sor of 4 (N = baud rate divisor +1). This produces a baud
clock of:
(
5
脳10 )
BR
= --------------------------------- = 9615.385
(
16
脳
5
脳
6.5
)
%error =
(
9615.385 鈥?9600
)
= 0.16
---------------------------------------------
9600
Note that the percent error is much lower than would be pos-
sible without the non-integer prescaler factor. Refer to the ta-
ble below for more examples.
System
Clock
4 MHz
5 MHz
10 MHz
Desired
Baud Rate
9600
9600
19200
N
P
Actual
Baud Rate
9615.385
9615.385
19230.769
Percent
Error
0.16
0.16
0.16
6
2 13
5 6.5
5 6.5
77
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