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CR16MCS5VJI8 Datasheet

  • CR16MCS5VJI8

  • Family of 16-bit CAN-enabled CompactRISC Microcontrollers

  • 713.21KB

  • 156页

  • NSC

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19.2.1
Master Mode
An ACCESS.bus transaction starts with a master device re-
questing bus mastership. It sends a Start Condition, followed
by the address of the device it wants to access. If this trans-
action is successfully completed, the software can assume
that the device has become the bus master.
For a device to become the bus master, the software should
perform the following steps:
1. Set ACBCTL1.START, and configure ACBCTL1.INTEN
to the desired operation mode (Polling or Interrupt). This
causes the ACB to issue a Start Condition on the AC-
CESS.bus, as soon as the ACCESS.bus is free
(ACBCST.BB=0). It then stalls the bus by holding SCL
low.
2. If a bus conflict is detected, (i.e., some other device pulls
down the SCL signal before this device does), ACB-
ST.BER is set.
3. If there is no bus conflict, ACBST.MASTER and ACB-
ST.SDAST are set.
4. If ACBCTL1.INTEN is set, and either ACBST.BER or
ACBST.SDAST is set, an interrupt is sent to the ICU.
Sending the Address Byte
Once this device is the active master of the ACCESS.bus
(ACBST.MASTER is set), it can send the address on the bus.
The address sent should not be this device鈥檚 own address as
defined in ACBADDR.ADDR if ACBADDR.SAEN is set, nor
should it be the global call address if ACBST.GCMTCH is set.
To send the address byte use the following sequence:
1. Configure the ACBCTL1.INTEN bit according to the de-
sired operation mode. For a receive transaction where
the software wants only one byte of data, it should set
the ACBCTL1.ACK bit.
If only an address needs to be sent, set (1) the
ACBCTL1.STASTRE bit.
2. Write the address byte (7-bit target device address), and
the direction bit, to the ACBSDA register. This causes
the module to generate a transaction. At the end of this
transaction, the acknowledge bit received is copied to
ACBST.NEGACK. During the transaction the SDA and
SCL lines are continuously checked for conflict with oth-
er devices. If a conflict is detected, the transaction is
aborted, ACBST.BER is set, and ACBST.MASTER is
cleared.
3. If ACBCTL1.STASTRE is set, and the transaction was
successfully completed (i.e., both ACBST.BER and
ACBST.NEGACK are cleared), ACBST.STASTR is set.
In this case, the ACB stalls any further ACCESS.bus op-
erations (i.e., holds SCL low). If ACBCTL1.INTE is set, it
also sends an interrupt to the core.
4. If the requested direction is transmit, and the start trans-
action was completed successfully (i.e., neither ACB-
ST.NEGACK nor ACBST.BER is set, and no other
master has accessed the device), ACBST.SDAST is set
to indicate that the module awaits attention.
5. If the requested direction is receive, the start transaction
was completed successfully and ACBCTL1.STASTRE is
cleared, the module starts receiving the first byte auto-
matically.
6. Check that both ACBST.BER and ACBST.NEGACK are
cleared. If the ACBCTL1.INTEN bit is set, an interrupt is
generated when either ACBST.BER or ACB-
ST.NEGACK is set.
Master Transmit
After becoming the bus master, the device can start transmit-
ting data on the ACCESS.bus.
To transmit a byte, the software should:
1. Check that the BER and NEGACK bits in ACBST are
cleared and ACBST.SDAST is set. Also, if
ACBCTL1.STASTRE is set, check that ACBST.STASTR
is cleared.
2. Write the data byte to be transmitted to the ACBSDA
register.
When the slave responds with a negative acknowledge, the
ACBST.NEGACK bit is set and the ACBST.SDAST bit re-
mains cleared. In this case, if ACBCTL1.INTEN is set, an in-
terrupt is sent to the core.
Master Receive
After becoming the bus master, the device can start receiving
data on the ACCESS.bus.
To receive a byte, the software should:
1. Check that ACBST.SDAST is set and ACBST.BER is
cleared. Also, if ACBCTL1.STASTRE is set, check that
ACBST.STASTR is cleared.
2. Set the ACBCTL1.ACK bit to 1, if the next byte is the last
byte that should be read. This causes a negative ac-
knowledge to be sent.
3. Read the data byte from the ACBSDA register.
Master Stop
A Stop Condition may be issued only when this device is the
active bus master (ACBST.MASTRER=1). To end a transac-
tion, set (1) ACBCTL1.STOP before clearing the current stall
flag (i.e., ACBST.SDAST, ACBST.NEGACK or ACB-
ST.STASTR). This causes the module to send a Stop Condi-
tion immediately, and clear ACBCTL1.STOP.
Master Bus Stall
The ACB module can stall the ACCESS.bus between trans-
fers while waiting for the core鈥檚 response. The ACCESS.bus
is stalled by holding the SCL signal low after the acknowl-
edge cycle. Note that this is interpreted as the beginning of
the following bus operation. The user must make sure that
the next operation is prepared before the flag that causes the
bus stall is cleared.
The flags that can cause a stall in master mode are:
鈥?Negative acknowledge after sending a byte (ACBST-
NEGACK=1).
鈥?ACBST.SDAST bit is set.
鈥?If ACBCTL1.STASTRE=1, after a successful start
(ACBST.STASTR=1).
Repeated Start
A repeated start is performed when this device is already the
bus master (ACBST.MASTER is set). In this case the AC-
CESS.bus is stalled and the ACB is awaiting the core han-
dling due to: negative acknowledge (ACBST.NEGACK=1),
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