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DSPIC30F6011AT-20E/PF Datasheet

  • DSPIC30F6011AT-20E/PF

  • High Performance Digital Signal Controllers

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  • MICROCHIP   MICROCHIP

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dsPIC30F6011/6012/6013/6014
15.12.3
BAUD RATE GENERATOR
In I
2
C Master mode, the reload value for the BRG is
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to 鈥?鈥?and
stops until another reload has taken place. If clock arbi-
tration is taking place, for instance, the BRG is reloaded
when the SCL pin is sampled high.
As per the I
2
C standard, FSCK may be 100 kHz or
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of 鈥?鈥?or 鈥?鈥?are illegal.
If a Start, RESTART, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are de-
asserted, and the respective control bits in the I2CCON
register are cleared to 鈥?鈥? When the user services the
bus collision Interrupt Service Routine, and if the I
2
C
bus is free, the user can resume communication by
asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit will
be set.
A write to the I2CTRN will start the transmission of data
at the first data bit regardless of where the transmitter
left off when bus collision occurred.
In a multi-master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
2
C
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
EQUATION 15-1:
SERIAL CLOCK RATE
FSCK = F
CY
/ I2CBRG
15.12.4
CLOCK ARBITRATION
Clock arbitration occurs when the master de-asserts
the SCL pin (SCL allowed to float high) during any
receive, transmit, or RESTART/Stop condition. When
the SCL pin is allowed to float high, the baud rate gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the baud rate generator is reloaded with the
contents of I2CBRG and begins counting. This ensures
that the SCL high time will always be at least one BRG
rollover count in the event that the clock is held low by
an external device.
15.13 I
2
C Module Operation During CPU
Sleep and Idle Modes
15.13.1
I
2
C OPERATION DURING CPU
SLEEP MODE
15.12.5
MULTI-MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION
Multi-master operation support is achieved by bus arbi-
tration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a 鈥?鈥?on SDA by letting SDA float high
while another master asserts a 鈥?鈥? When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a 鈥?鈥?and the data sampled on the SDA
pin =
0,
then a bus collision has taken place. The
master will set the MI2CIF pulse and reset the master
portion of the I
2
C port to its Idle state.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are de-asserted and a
value can now be written to I2CTRN. When the user
services the I
2
C master event Interrupt Service Rou-
tine, if the I
2
C bus is free (i.e., the P bit is set), the user
can resume communication by asserting a Start
condition.
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic 鈥?鈥? If
Sleep occurs in the middle of a transmission and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
15.13.2
I
2
C OPERATION DURING CPU IDLE
MODE
For the I
2
C, the I2CSIDL bit selects if the module will
stop on Idle or continue on Idle. If I2CSIDL =
0,
the
module will continue operation on assertion of the Idle
mode. If I2CSIDL =
1,
the module will stop on Idle.
DS70117C-page 98
Preliminary
铮?/div>
2004 Microchip Technology Inc.

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