DSPIC30F6011AT-20E/PF Datasheet

  • DSPIC30F6011AT-20E/PF

  • High Performance Digital Signal Controllers

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  • 222页

  • MICROCHIP   MICROCHIP

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dsPIC30F6011/6012/6013/6014
2.3
Divide Support
The dsPIC devices feature a 16/16-bit signed fractional
divide operation, as well as 32/16-bit and 16/16-bit
signed and unsigned integer divide operations, in the
form of single instruction iterative divides. The following
instructions and data sizes are supported:
1.
2.
3.
4.
5.
DIVF
- 16/16 signed fractional divide
DIV.sd
- 32/16 signed divide
DIV.ud
- 32/16 unsigned divide
DIV.sw
- 16/16 signed divide
DIV.uw
- 16/16 unsigned divide
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the
REPEAT
instruc-
tion as shown in Table 2-1 (REPEAT will execute the tar-
get instruction {operand value+1} times). The REPEAT
loop count must be setup for 18 iterations of the
DIV/
DIVF
instruction. Thus, a complete divide operation
requires 19 cycles.
Note:
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
Instruction
DIVF
DIV.sd
DIV.sw or
DIV.s
DIV.ud
DIV.uw or
DIV.u
DIVIDE INSTRUCTIONS
Function
Signed fractional divide: Wm/Wn
鈫?/div>
W0; Rem
鈫?/div>
W1
Signed divide: (Wm+1:Wm)/Wn
鈫?/div>
W0; Rem
鈫?/div>
W1
Signed divide: Wm/Wn
鈫?/div>
W0; Rem
鈫?/div>
W1
Unsigned divide: (Wm+1:Wm)/Wn
鈫?/div>
W0; Rem
鈫?/div>
W1
Unsigned divide: Wm/Wn
鈫?/div>
W0; Rem
鈫?/div>
W1
DS70117C-page 16
Preliminary
铮?/div>
2004 Microchip Technology Inc.

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