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DSPIC30F6011AT-20E/PF Datasheet

  • DSPIC30F6011AT-20E/PF

  • High Performance Digital Signal Controllers

  • 3527.50KB

  • 222页

  • MICROCHIP   MICROCHIP

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dsPIC30F6011/6012/6013/6014
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bit MCU code. Should a mis-
aligned read or write be attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write will not occur. In either case, a trap will then
be executed, allowing the system and/or user to exam-
ine the machine state prior to execution of the address
fault.
3.2.6
SOFTWARE STACK
The dsPIC devices contain a software stack. W15 is
used as the stack pointer.
The stack pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops and
post-increments for stack pushes as shown in Figure 3-
11. Note that for a PC push during any
CALL
instruc-
tion, the MSB of the PC is zero-extended before the
push, ensuring that the MSB is always clear.
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
FIGURE 3-10:
15
0001
0003
0005
DATA ALIGNMENT
87
LS Byte
Byte 0
Byte 2
Byte 4
0
0000
0002
0004
MS Byte
Byte1
Byte3
Byte5
All byte loads into any W register are loaded into the LS
Byte. The MSB is not modified.
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
There is a Stack Pointer Limit register (SPLIM) associ-
ated with the stack pointer. SPLIM is uninitialized at
Reset. As is the case for the stack pointer, SPLIM<0>
is forced to 鈥?鈥?because all stack operations must be
word aligned. Whenever an effective address (EA) is
generated using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a Stack Error Trap will not
occur. The Stack Error Trap will occur on a subsequent
push operation. Thus, for example, if it is desirable to
cause a Stack Error Trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.
Similarly, a stack pointer underflow (stack error) trap is
generated when the stack pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
3.2.5
NEAR DATA SPACE
Stack Grows Towards
Higher Address
An 8-Kbyte 鈥榥ear鈥?data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using
MOV
instructions, which
support memory direct addressing with a 16-bit
address field.
FIGURE 3-11:
0x0000
15
CALL
STACK FRAME
0
PC<15:0>
000000000
PC<22:16>
<Free Word>
W15 (before
CALL)
W15 (after
CALL)
POP : [--W15]
PUSH : [W15++]
铮?/div>
2004 Microchip Technology Inc.
Preliminary
DS70117C-page 33

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