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DSPIC30F6011AT-20E/PF Datasheet

  • DSPIC30F6011AT-20E/PF

  • High Performance Digital Signal Controllers

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  • 222页

  • MICROCHIP   MICROCHIP

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dsPIC30F6011/6012/6013/6014
7.0
DATA EEPROM MEMORY
The Data EEPROM Memory is readable and writable
during normal operation over the entire V
DD
range. The
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory, as well. As described in Section 6.5, these
registers are:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
NVMCON
NVMADR
NVMADRU
NVMKEY
Control bit WR initiates write operations similar to pro-
gram Flash writes. This bit cannot be cleared, only set,
in software. They are cleared in hardware at the com-
pletion of the write operation. The inability to clear the
WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal opera-
tion. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register NVMADR remains unchanged.
Note:
Interrupt flag bit NVMIF in the IFS0 regis-
ter is set when write is complete. It must be
cleared in software.
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR in conjunction with the
NVMADRU register are used to address the EEPROM
location being accessed.
TBLRDL
and
TBLWTL
instructions are used to read and write data EEPROM.
The dsPIC30F devices have up to 8 Kbytes (4K
words) of data EEPROM with an address range from
0x7FF000
to
0x7FFFFE.
A word write operation should be preceded by an erase
of the corresponding memory location(s). The write typ-
ically requires 2 ms to complete but the write time will
vary with voltage and temperature.
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
7.1
Reading the Data EEPROM
A
TBLRD
instruction reads a word at the current pro-
gram word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4 as shown in Example 7-1.
EXAMPLE 7-1:
MOV
MOV
MOV
TBLRDL
DATA EEPROM READ
#LOW_ADDR_WORD,W0 ; Init Pointer
#HIGH_ADDR_WORD,W1
W1
,
TBLPAG
[ W0 ], W4
; read data EEPROM
铮?/div>
2004 Microchip Technology Inc.
Preliminary
DS70117C-page 55

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