您的位置：维库电子市场网 > Datasheet > DSPIC30F6011AT-20E/PF

DSPIC30F6011AT-20E/PF Datasheet

  • DSPIC30F6011AT-20E/PF

  • High Performance Digital Signal Controllers

  • 3527.50KB

  • 222页

  • MICROCHIP   MICROCHIP

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

dsPIC30F6011/6012/6013/6014
9.0
TIMER1 MODULE
This section describes the 16-bit General Purpose
(GP) Timer1 module and associated Operational
modes. Figure 9-1 depicts the simplified block diagram
of the 16-bit Timer1 module.
The following sections provide a detailed description
including setup and control registers, along with asso-
ciated block diagrams for the Operational modes of the
timers.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the real-time clock, or operate as a
free-running interval timer/counter. The 16-bit timer has
the following modes:
鈥?16-bit Timer
鈥?16-bit Synchronous Counter
鈥?16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
鈥?Timer gate operation
鈥?Selectable prescaler settings
鈥?Timer operation during CPU Idle and Sleep
modes
鈥?Interrupt on 16-bit Period register match or falling
edge of external gate signal
These Operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
presents a block diagram of the 16-bit timer module.
16-bit Timer Mode:
In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value preloaded into the Period register PR1, then
resets to 鈥?鈥?and continues to count.
When the CPU goes into the Idle mode, the timer will
stop incrementing unless the TSIDL (T1CON<13>)
bit =
0.
If TSIDL =
1,
the timer module logic will resume
the incrementing sequence upon termination of the
CPU Idle mode.
16-bit Synchronous Counter Mode:
In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to 鈥?鈥?and continues.
When the CPU goes into the Idle mode, the timer will
stop incrementing unless the respective TSIDL bit =
0.
If TSIDL =
1,
the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.
16-bit Asynchronous Counter Mode:
In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to 鈥?鈥?and continues.
When the timer is configured for the Asynchronous
mode of operation and the CPU goes into the Idle
mode, the timer will stop incrementing if TSIDL =
1.
FIGURE 9-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
PR1
Equal
Comparator x 16
TSYNC
1
Sync
Reset
T1IF
Event Flag
0
1
TGATE
TMR1
0
Q
Q
D
CK
TGATE
TCS
TGATE
SOSCO/
T1CK
LPOSCEN
SOSCI
T
CY
Gate
Sync
TON
1x
01
00
TCKPS<1:0>
2
Prescaler
1, 8, 64, 256
铮?/div>
2004 Microchip Technology Inc.
Preliminary
DS70117C-page 67

DSPIC30F6011AT-20E/PF相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！