您的位置：维库电子市场网 > Datasheet > DSPIC30F6011AT-20E/PF

DSPIC30F6011AT-20E/PF Datasheet

  • DSPIC30F6011AT-20E/PF

  • High Performance Digital Signal Controllers

  • 3527.50KB

  • 222页

  • MICROCHIP   MICROCHIP

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

dsPIC30F6011/6012/6013/6014
15.2
I
2
C Module Addresses
The I2CADD register contains the Slave mode
addresses. The register is a 10-bit register.
If the A10M bit (I2CCON<10>) is 鈥?鈥? the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the 7 LS bits of
the I2CADD register.
If the A10M bit is 鈥?鈥? the address is assumed to be a
10-bit address. When an address is received, it will be
compared with the binary value 鈥?1110
A9 A8鈥?/div>
(where
A9
and
A8
are two Most Significant bits of I2CADD). If
that value matches, the next address will be compared
with the Least Significant 8 bits of I2CADD, as specified
in the 10-bit addressing protocol.
7-bit I
2
C Slave Addresses supported by dsPIC30F:
0x00
0x01-0x03
0x04-0x77
0x78-0x7b
0x7c-0x7f
General call address or start byte
Reserved
Valid 7-bit addresses
Valid 10-bit addresses (lower 7
bits)
Reserved
received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK is sent on the
ninth clock.
If the RBF flag is set, indicating that I2CRCV is still
holding data from a previous operation (RBF =
1),
then
ACK is not sent; however, the interrupt pulse is gener-
ated. In the case of an overflow, the contents of the
I2CRSR are not loaded into the I2CRCV.
Note:
The I2CRCV will be loaded if the I2COV
bit =
1
and the RBF flag =
0.
In this case,
a read of the I2CRCV was performed but
the user did not clear the state of the
I2COV bit before the next receive
occurred. The Acknowledgement is not
sent (ACK =
1)
and the I2CRCV is
updated.
15.4
I
2
C 10-bit Slave Mode Operation
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match is more complex.
The I
2
C specification dictates that a slave must be
addressed for a write operation with two address bytes
following a Start bit.
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a 7-bit
address. The address detection protocol for the first byte
of a message address is identical for 7-bit and 10-bit
messages, but the bits being compared are different.
I2CADD holds the entire 10-bit address. Upon receiv-
ing an address following a Start bit, I2CRSR <7:3> is
compared against a literal 鈥?1110鈥?(the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs and if R_W =
0,
the
interrupt pulse is sent. The ADD10 bit will be cleared to
indicate a partial address match. If a match fails or
R_W =
1,
the ADD10 bit is cleared and the module
returns to the Idle state.
The low byte of the address is then received and com-
pared with I2CADD<7:0>. If an address match occurs,
the interrupt pulse is generated and the ADD10 bit is
set, indicating a complete 10-bit address match. If an
address match did not occur, the ADD10 bit is cleared
and the module returns to the Idle state.
15.3
I
2
C 7-bit Slave Mode Operation
Once enabled (I2CEN =
1),
the slave module will wait
for a Start bit to occur (i.e., the I
2
C module is 鈥業dle鈥?. Fol-
lowing the detection of a Start bit, 8 bits are shifted into
I2CRSR and the address is compared against
I2CADD. In 7-bit mode (A10M =
0),
bits I2CADD<6:0>
are compared against I2CRSR<7:1> and I2CRSR<0>
is the R_W bit. All incoming bits are sampled on the ris-
ing edge of SCL.
If an address match occurs, an Acknowledgement will
be sent, and the slave event interrupt flag (SI2CIF) is
set on the falling edge of the ninth (ACK) bit. The
address match does not affect the contents of the
I2CRCV buffer or the RBF bit.
15.3.1
SLAVE TRANSMISSION
If the R_W bit received is a 鈥?鈥? then the serial port will
go into Transmit mode. It will send ACK on the ninth bit
and then hold SCL to 鈥?鈥?until the CPU responds by writ-
ing to I2CTRN. SCL is released by setting the SCLREL
bit, and 8 bits of data are shifted out. Data bits are
shifted out on the falling edge of SCL, such that SDA is
valid during SCL high. The interrupt pulse is sent on the
falling edge of the ninth clock pulse, regardless of the
status of the ACK received from the master.
15.4.1
10-BIT MODE SLAVE
TRANSMISSION
15.3.2
SLAVE RECEPTION
If the R_W bit received is a 鈥?鈥?during an address
match, then Receive mode is initiated. Incoming bits
are sampled on the rising edge of SCL. After 8 bits are
Once a slave is addressed in this fashion with the full
10-bit address (we will refer to this state as
鈥淧RIOR_ADDR_MATCH鈥?, the master can begin
sending data bytes for a slave reception operation.
铮?/div>
2004 Microchip Technology Inc.
Preliminary
DS70117C-page 95

DSPIC30F6011AT-20E/PF相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！