ELANSC300-33KI Datasheet

  • ELANSC300-33KI

  • Highly Integrated, Low-Power, 32-Bit Microcontroller

  • 1344.13KB

  • 139页

  • AMD

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P R E L I M I N A R Y
Table 9. Display Interface (Continued)
I/O
Type
O (I/I)
O
O (I/I)
O (I/I)
O (I/I)
O (I/I)
O (I/I)
O (I/I)
O (I/I)
O
I [B]
I [B]
I [B]
O [B]
Drive
Type
C
C
C
C
C
C
C
C
B
E
C
C
C
C
Reset State (volts)
Clock Off
0 (鈥?鈥?
0 (1/1)
0 (鈥?鈥?
0 (鈥?鈥?
0 (鈥?鈥?
0 (鈥?鈥?
0 (鈥?鈥?
0 (鈥?鈥?
1 (鈥?鈥?
1(0/1)
鈥?[0]
鈥?[0]
鈥?[0]
0[0]
Internal Local
CGA
Bus
0.0
3.3
0.0
0.0
0.0
0.0
0.0
0.0
3.3
3.3
3.3
3.3
0.0
0.0
0.0
3.3
3.3
3.3
3.3
0.0
0.0
3.3
3.3
3.3
3.3
3.3
0.0
0.0
Max
ISA
0.0
5.0
0.0
3.3
3.3
3.3
3.3
3.3
3.3
5.0
3.3
3.3
0.0
0.0
VCCIO
VCC1
VSYS2
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VSYS2
VCC1
VCC1
VCC1
VSYS2
VCC
Clamp
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
Spec.
Load
(pF)
100
100
100
100
100
100
100
100
50
50
70
70
70
70
Signal Name
LCDD3
(DRQ1 / DRQ1)
LCDD0 (DACK5/
DACK5)
LCDD1 (DRQ5/
DRQ5)
LCDD2 (IOCHCHK/
IOCHCHK)
M (IRQ4/IRQ4)
CP1 (PULLDN/IRQ5)
CP2 (PULLUP/
IRQ10)
FRM (IRQ12/IRQ12)
LVEE (IRQ15/
IRQ15)
LVDD (A12/ BALE)
IOCS16 [LCDDL0]
MCS16 [LCDDL1]
IRQ14 [LCDDL2]
SBHE [LCDDL3]
Pin No.
174
144
175
177
173
178
179
181
182
145
196
197
198
143
Term
Notes:
1. LS in the
Clock Off
column stands for Last State.
2. Reset State Local Bus signal loading 920 mV鈥? V. For 33-MHz operation, CPUCLK loading = 30 pF.
All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
32
脡lan鈩C300 Microcontroller Data Sheet

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