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ELANSC300-33KI Datasheet

  • ELANSC300-33KI

  • Highly Integrated, Low-Power, 32-Bit Microcontroller

  • 1344.13KB

  • 139页

  • AMD

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P R E L I M I N A R Y
POWER MANAGEMENT INTERFACE
ACIN
AC Input Status (Input; Active High)
When asserted, this signal disables all power manage-
ment functions (if so enabled). It can be used to indi-
cate when the system is being supplied power from an
AC source.
BL4鈥揃L1
register bit if configured to do so. PGP2 and PGP3 can
also be configured for a specific state when the PMU is
in the off state.
PGP2 and PGP3 can be programmed to be set to a
pre-defined state for Micro Power Off mode.
For more information about PGP3鈥揚GP0, see the
脡lan
TM
SC300 Microcontroller Programmer鈥檚 Refer-
ence Manual
, order #18470B and
Using 10-Bit
ROMCS Designs in 脡lan
TM
SC300 and 脡lanSC310 Mi-
crocontrollers Application Note
, order #21825.
PMC4鈥揚MC0
Battery Low Detects
(Inputs; Negative Edge Sensitive)
These signals are used to indicate to the 脡lanSC300
microcontroller the current status of the battery. BL4鈥?/div>
BL1 can indicate various conditions of the battery as
status changes. A High indicates normal operating
conditions, while a Low indicates a low voltage warning
condition. These inputs can be used to force the sys-
tem into one of the power saving modes when acti-
vated, as follows:
n
BL1 can be programmed to force the system to go
to Low Speed PLL mode or to generate an SMI.
n
BL2 can be programmed to force the system to
enter Sleep mode if not already in Sleep mode, or
to generate an SMI.
n
BL3 can only be programmed to generate an SMI.
n
BL4 can be programmed to force the system to
enter Suspend mode.
EXTSMI
Power Management Controls
(Output; Programmable)
Power Management Control outputs control the power
to various external devices and system components.
The PMC0, PMC1, PMC2, and PMC4 signals are as-
serted Low immediately after reset, and the PMC3 sig-
nal is asserted High immediately after reset. Each of
the PMC pins can then be programmed to be High or
Low for each of the 脡lanSC300 microcontroller power
management modes.
SUS/RES
Suspend/Resume Operation (Input; Rising Edge)
When the 脡lanSC300 microcontroller is in High Speed
PLL, Low Speed PLL, or Doze mode, a positive edge
on this pin causes the internal logic to step down
through the Power Management modes (one per re-
fresh cycle) until Sleep mode is entered. If in Sleep,
Suspend, or Off mode, a positive edge on this pin
causes the 脡lanSC300 microcontroller to enter the
High Speed PLL mode.
External System Management Interrupt
(Input; Edge Sensitive)
This input is provided to allow external logic to gener-
ate an SMI request to the CPU. It is edge triggered,
with the polarity programmable.
LPH
Latched Power Control (Output; Active Low)
This signal is the inverse of BL4 if ACIN is not true and
BL4 is enabled.
PGP3鈥揚GP0
DISPLAY INTERFACE
The signals listed as part of the display interface are
only available when the 脡lanSC300 microcontroller is
configured with the internal LCD controller enabled. If
the internal LCD controller is disabled, the functions of
these pins change to support either a CPU local bus in-
terface or maximum ISA bus interface. The pins re-
quired for physical connection to the microcontroller
are listed at the end of this section on page 42. For
more information about the LCD controller, see the
Configuring the 脡lan
TM
SC300 Device鈥檚 Internal CGA
Controller for a Specific LCD Panel Application Note
,
order #20749.
Programmable Chip Select Generation
(Input/Output)
PGP0 and PGP1 can be programmed as input or out-
put. The default is input. PGP2 and PGP3 are output
only.
These general purpose pins can be individually pro-
grammed as decoder outputs or chip selects for other
external peripheral devices.
PGP0 and PGP2 can be gated with I/O write or act as
an address decode only. PGP1 and PGP3 can be
gated with I/O Read or act as an address decode only.
PGP0 and PGP1 can be directly controlled via a single
40
脡lan鈩C300 Microcontroller Data Sheet

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