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ELANSC300-33KI Datasheet

  • ELANSC300-33KI

  • Highly Integrated, Low-Power, 32-Bit Microcontroller

  • 1344.13KB

  • 139页

  • AMD

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P R E L I M I N A R Y
CP1
LCDD1
LCD Panel Line Clock (Output)
This is the Line Clock when in internal LCD mode and
an LCD configuration is selected. It is activated at the
start of every pixel line refresh cycle. CP1 should be
connected to the equivalent line on the LCD panel.
CP2
LCD Data Bit (Output)
When in internal LCD mode and an LCD configuration
is selected, this signal is data bit 1. LCDD1 should be
connected to the corresponding pin on the LCD panel.
LCDD2
LCD Data Bit (Output)
When in internal LCD mode and an LCD configuration
is selected, this signal is data bit 2. LCDD2 should be
connected to the corresponding pin on the LCD panel.
LCDD3
LCD Panel Shift Clock (Output)
This is the nibble/byte strobe when in internal LCD
mode and an LCD configuration is selected. CP2 is
also known as the shift clock or data shift. It is used by
the LCD to latch data. CP2 should be connected to the
equivalent line on the LCD panel.
DSCE
LCD Data Bit (Output)
When in internal LCD mode and an LCD configuration
is selected, this signal is data bit 3. LCDD3 is the MSB
and should be connected to the corresponding MSB
pin on the LCD panel.
[LCDDL3鈥揕CDDL0]
Display SRAM Chip Enable (Output; Active Low)
This signal generates the external video SRAM Chip
Enable.
DSMA14鈥揇SMA0
Display SRAM Address Bus (Output)
These signals generate the address to the SRAM. Up
to 32 Kbyte can be supported for the display interface.
DSMD7鈥揇SMD0
LCD Panel Data Bits for Dual-Scan Panels
(Outputs)
When the 脡lanSC300 microcontroller is programmed
to support LCD Dual-Scan Panel mode (separate data
bits for the top and bottom half of the panel), these bits
(LCDDL3鈥揕CDDL0) are for the bottom half of the
screen. LCDD3鈥揕CDD0 are the data bits for the top
half of the screen. LCD Dual-Scan Panel mode is se-
lected via firmware. LCDDL0 is the LSB for the lower
panel and LCDDL3 is the MSB for the lower panel.
These pins are shared with IOCS16, MCS16, IRQ14,
and SBHE (described in 鈥淪ystem Interface鈥? beginning
on page 35.) LCDDL3鈥揕CDDL0 should be connected
to their corresponding pins on the dual-screen LCD
lower panel.
LVDD
Display SRAM Data Bus (Bidirectional)
These signals provide the data bus used for the video
SRAM.
DSOE
Display SRAM Output Enable (Output; Active Low)
This signal controls the video SRAM Output Enable
pin.
DSWE
Display SRAM Write Enable (Output; Active Low)
When asserted, this signal indicates a Write to the
video SRAM.
FRM
LCD Panel VDD Voltage Control
(Output; Active Low)
This signal is used to control the assertion of the LCD鈥檚
VDD driver. LVDD is provided to be part of the solution
in sequencing the panel鈥檚 VDD, DATA, and VEE sig-
nals in the proper order.
LVEE
LCD Panel Line Frame Start (Output)
This signal is asserted at the start of every frame (panel
scan) when in LCD mode and an LCD configuration is
selected. FRM is also known as FLM or frame. It should
be connected to the equivalent line on the LCD panel.
LCDD0
LCD Panel VEE Voltage Control
(Output; Active Low)
This signal is used to control the assertion of the LCD鈥檚
VEE driver. LVEE is provided to be part of the solution
in sequencing the panel鈥檚 VDD, DATA, and VEE sig-
nals in the proper order.
LCD Data Bit (Output)
When in internal LCD mode and an LCD configuration
is selected, this signal is data bit 0. LCDD0 is the LSB
and should be connected to the corresponding LSB pin
on the LCD panel.
脡lan鈩C300 Microcontroller Data Sheet
41

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